#define NGBE_FRAME_SIZE_MAX (9728) /* Maximum frame size, +FCS */
#define NGBE_FRAME_SIZE_DFT (1522) /* Default frame size, +FCS */
#define NGBE_NUM_POOL (32)
+#define NGBE_PBRXSIZE_MAX 0x00080000 /* 512KB Packet Buffer */
+#define NGBE_PBTXSIZE_MAX 0x00005000 /* 20KB Packet Buffer */
+#define NGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
#define NGBE_MAX_QP (8)
#define NGBE_MAX_UTA 128
+#define NGBE_PCI_MASTER_DISABLE_TIMEOUT 800
+
+
#define NGBE_ALIGN 128 /* as intel did */
#define NGBE_ISB_SIZE 16
ngbe_eeprom_none /* No NVM support */
};
+enum ngbe_link_type {
+ ngbe_link_type_unknown = 0,
+ ngbe_link_fiber,
+ ngbe_link_copper
+};
+
enum ngbe_mac_type {
ngbe_mac_unknown = 0,
ngbe_mac_em,
s32 (*get_link_capabilities)(struct ngbe_hw *hw,
u32 *speed, bool *autoneg);
+ /* Packet Buffer manipulation */
+ void (*setup_pba)(struct ngbe_hw *hw);
+
/* LED */
s32 (*led_on)(struct ngbe_hw *hw, u32 index);
s32 (*led_off)(struct ngbe_hw *hw, u32 index);
s32 (*check_overtemp)(struct ngbe_hw *hw);
enum ngbe_mac_type type;
+ enum ngbe_link_type link_type;
u8 addr[ETH_ADDR_LEN];
u8 perm_addr[ETH_ADDR_LEN];
#define NGBE_MAX_MTA 128
u32 mcft_size;
u32 vft_size;
u32 num_rar_entries;
+ u32 rx_pb_size;
u32 max_tx_queues;
u32 max_rx_queues;
bool get_link_status;
bool autoneg_wait_to_complete);
s32 (*check_link)(struct ngbe_hw *hw, u32 *speed, bool *link_up);
s32 (*set_phy_power)(struct ngbe_hw *hw, bool on);
+ s32 (*led_oem_chk)(struct ngbe_hw *hw, u32 *data);
s32 (*get_adv_pause)(struct ngbe_hw *hw, u8 *pause_bit);
s32 (*get_lp_adv_pause)(struct ngbe_hw *hw, u8 *pause_bit);
s32 (*set_pause_adv)(struct ngbe_hw *hw, u16 pause_bit);
u32 q_tx_regs[8 * 4];
bool offset_loaded;
bool is_pf;
+ bool gpio_ctl;
+ u32 led_conf;
struct {
u64 rx_qp_packets;
u64 tx_qp_packets;