octeontx_port_open(struct octeontx_nic *nic)
{
octeontx_mbox_bgx_port_conf_t bgx_port_conf;
+ octeontx_mbox_bgx_port_fifo_cfg_t fifo_cfg;
int res;
res = 0;
nic->mcast_mode = bgx_port_conf.mcast_mode;
nic->speed = bgx_port_conf.mode;
+ memset(&fifo_cfg, 0x0, sizeof(fifo_cfg));
+
+ res = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg);
+ if (res < 0) {
+ octeontx_log_err("failed to get port %d fifo cfg", res);
+ return res;
+ }
+
+ nic->fc.rx_fifosz = fifo_cfg.rx_fifosz;
+
memcpy(&nic->mac_addr[0], &bgx_port_conf.macaddr[0],
RTE_ETHER_ADDR_LEN);
struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);
uint16_t flags = 0;
+ if (nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
+ nic->tx_offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
+ flags |= OCCTX_TX_OFFLOAD_OL3_OL4_CSUM_F;
+
+ if (nic->tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM ||
+ nic->tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM ||
+ nic->tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM ||
+ nic->tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)
+ flags |= OCCTX_TX_OFFLOAD_L3_L4_CSUM_F;
+
if (!(nic->tx_offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
flags |= OCCTX_TX_OFFLOAD_MBUF_NOFF_F;
octeontx_rx_offload_flags(struct rte_eth_dev *eth_dev)
{
struct octeontx_nic *nic = octeontx_pmd_priv(eth_dev);
- struct rte_eth_dev_data *data = eth_dev->data;
- struct rte_eth_conf *conf = &data->dev_conf;
- struct rte_eth_rxmode *rxmode = &conf->rxmode;
uint16_t flags = 0;
- if (rxmode->mq_mode == ETH_MQ_RX_RSS)
- flags |= OCCTX_RX_OFFLOAD_RSS_F;
+ if (nic->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM))
+ flags |= OCCTX_RX_OFFLOAD_CSUM_F;
+
+ if (nic->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
+ flags |= OCCTX_RX_OFFLOAD_CSUM_F;
if (nic->rx_offloads & DEV_RX_OFFLOAD_SCATTER) {
flags |= OCCTX_RX_MULTI_SEG_F;
rte_event_dev_close(nic->evdev);
+ octeontx_dev_flow_ctrl_fini(dev);
+
octeontx_dev_vlan_offload_fini(dev);
ret = octeontx_pko_channel_close(nic->base_ochan);
octeontx_recheck_rx_offloads(rxq);
dev->data->rx_queues[qidx] = rxq;
dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
+
return 0;
}
.dev_supported_ptypes_get = octeontx_dev_supported_ptypes_get,
.mtu_set = octeontx_dev_mtu_set,
.pool_ops_supported = octeontx_pool_ops,
+ .flow_ctrl_get = octeontx_dev_flow_ctrl_get,
+ .flow_ctrl_set = octeontx_dev_flow_ctrl_set,
};
/* Create Ethdev interface per BGX LMAC ports */
/* Update same mac address to BGX CAM table at index 0 */
octeontx_bgx_port_mac_add(nic->port_id, nic->mac_addr, 0);
+ res = octeontx_dev_flow_ctrl_init(eth_dev);
+ if (res < 0)
+ goto err;
+
PMD_INIT_LOG(DEBUG, "ethdev info: ");
PMD_INIT_LOG(DEBUG, "port %d, port_ena %d ochan %d num_ochan %d tx_q %d",
nic->port_id, nic->port_ena,
free_mac_addrs:
rte_free(data->mac_addrs);
+ data->mac_addrs = NULL;
err:
if (nic)
octeontx_port_close(nic);