{
uint64_t capa = NIX_RX_OFFLOAD_CAPA;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf(dev) ||
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
return capa;
dev->cints = rsp->cints;
dev->qints = rsp->qints;
dev->npc_flow.channel = dev->rx_chan_base;
+ dev->ptp_en = rsp->hw_rx_tstamp_en;
return 0;
}
{
struct otx2_mbox *mbox = dev->mbox;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf_or_sdp(dev))
return 0;
otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
{
struct otx2_mbox *mbox = dev->mbox;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf_or_sdp(dev))
return 0;
otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
{
struct otx2_mbox *mbox = dev->mbox;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf_or_sdp(dev))
return 0;
otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
{
struct otx2_mbox *mbox = dev->mbox;
- if (otx2_dev_is_vf(dev))
- return 0;
+ if (en && otx2_dev_is_vf_or_sdp(dev))
+ return -ENOTSUP;
if (en)
otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
{
struct otx2_mbox *mbox = dev->mbox;
- if (otx2_dev_is_vf(dev))
+ if (otx2_dev_is_vf_or_sdp(dev))
return 0;
otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
struct rte_eth_rxmode *rxmode = &conf->rxmode;
uint16_t flags = 0;
- if (rxmode->mq_mode == ETH_MQ_RX_RSS)
+ if (rxmode->mq_mode == ETH_MQ_RX_RSS &&
+ (dev->rx_offloads & DEV_RX_OFFLOAD_RSS_HASH))
flags |= NIX_RX_OFFLOAD_RSS_F;
if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
flags |= NIX_RX_OFFLOAD_TSTAMP_F;
+ if (!dev->ptype_disable)
+ flags |= NIX_RX_OFFLOAD_PTYPE_F;
+
return flags;
}
goto fail_offloads;
}
+ if (dev->ptp_en &&
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+ otx2_err("Both PTP and switch header enabled");
+ goto free_nix_lf;
+ }
+
rc = nix_lf_switch_header_type_enable(dev);
if (rc) {
otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
if (rc) {
otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
- goto q_irq_fini;
+ goto cq_fini;
}
rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
if (rc) {
otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
- goto q_irq_fini;
+ goto cq_fini;
}
rc = otx2_nix_mc_addr_list_install(eth_dev);
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, i;
- if (eth_dev->data->nb_rx_queues != 0) {
+ /* MTU recalculate should be avoided here if PTP is enabled by PF, as
+ * otx2_nix_recalc_mtu would be invoked during otx2_nix_ptp_enable_vf
+ * call below.
+ */
+ if (eth_dev->data->nb_rx_queues != 0 && !otx2_ethdev_is_ptp_en(dev)) {
rc = otx2_nix_recalc_mtu(eth_dev);
if (rc)
return rc;
else
otx2_nix_timesync_disable(eth_dev);
+ /* Update VF about data off shifted by 8 bytes if PTP already
+ * enabled in PF owning this VF
+ */
+ if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
+ otx2_nix_ptp_enable_vf(eth_dev);
+
rc = npc_rx_enable(dev);
if (rc) {
otx2_err("Failed to enable NPC rx %d", rc);
.dev_set_link_up = otx2_nix_dev_set_link_up,
.dev_set_link_down = otx2_nix_dev_set_link_down,
.dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
+ .dev_ptypes_set = otx2_nix_ptypes_set,
.dev_reset = otx2_nix_dev_reset,
.stats_get = otx2_nix_dev_stats_get,
.stats_reset = otx2_nix_dev_stats_reset,
.xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
.rxq_info_get = otx2_nix_rxq_info_get,
.txq_info_get = otx2_nix_txq_info_get,
+ .rx_burst_mode_get = otx2_rx_burst_mode_get,
+ .tx_burst_mode_get = otx2_tx_burst_mode_get,
.rx_queue_count = otx2_nix_rx_queue_count,
.rx_descriptor_done = otx2_nix_rx_descriptor_done,
.rx_descriptor_status = otx2_nix_rx_descriptor_status,
return otx2_mbox_process(mbox);
}
+static bool
+otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
+{
+ if (pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_PF ||
+ pci_dev->id.device_id == PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+ return true;
+ return false;
+}
+
static int
otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
{
goto error;
}
}
+ if (otx2_eth_dev_is_sdp(pci_dev))
+ dev->sdp_link = true;
+ else
+ dev->sdp_link = false;
/* Device generic callbacks */
dev->ops = &otx2_dev_ops;
dev->eth_dev = eth_dev;
dev->configured = 0;
dev->drv_inited = true;
+ dev->ptype_disable = 0;
dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
PCI_DEVID_OCTEONTX2_RVU_AF_VF)
},
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_OCTEONTX2_RVU_SDP_PF)
+ },
+ {
+ RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+ PCI_DEVID_OCTEONTX2_RVU_SDP_VF)
+ },
{
.vendor_id = 0,
},