#include "otx2_ethdev.h"
-static inline void
-otx2_eth_set_rx_function(struct rte_eth_dev *eth_dev)
-{
- RTE_SET_USED(eth_dev);
-}
-
-static inline void
-otx2_eth_set_tx_function(struct rte_eth_dev *eth_dev)
-{
- RTE_SET_USED(eth_dev);
-}
-
static inline uint64_t
nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
{
static const struct otx2_dev_ops otx2_dev_ops = {
.link_status_update = otx2_eth_dev_link_status_update,
+ .ptp_info_update = otx2_eth_dev_ptp_info_update
};
static int
return otx2_mbox_process(mbox);
}
+int
+otx2_cgx_rxtx_start(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ if (otx2_dev_is_vf(dev))
+ return 0;
+
+ otx2_mbox_alloc_msg_cgx_start_rxtx(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+int
+otx2_cgx_rxtx_stop(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ if (otx2_dev_is_vf(dev))
+ return 0;
+
+ otx2_mbox_alloc_msg_cgx_stop_rxtx(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+static int
+npc_rx_enable(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ otx2_mbox_alloc_msg_nix_lf_start_rx(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+static int
+npc_rx_disable(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ otx2_mbox_alloc_msg_nix_lf_stop_rx(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+static int
+nix_cgx_start_link_event(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ if (otx2_dev_is_vf(dev))
+ return 0;
+
+ otx2_mbox_alloc_msg_cgx_start_linkevents(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+static int
+cgx_intlbk_enable(struct otx2_eth_dev *dev, bool en)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ if (otx2_dev_is_vf(dev))
+ return 0;
+
+ if (en)
+ otx2_mbox_alloc_msg_cgx_intlbk_enable(mbox);
+ else
+ otx2_mbox_alloc_msg_cgx_intlbk_disable(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
+static int
+nix_cgx_stop_link_event(struct otx2_eth_dev *dev)
+{
+ struct otx2_mbox *mbox = dev->mbox;
+
+ if (otx2_dev_is_vf(dev))
+ return 0;
+
+ otx2_mbox_alloc_msg_cgx_stop_linkevents(mbox);
+
+ return otx2_mbox_process(mbox);
+}
+
static inline void
nix_rx_queue_reset(struct otx2_eth_rxq *rxq)
{
aq->cq.cq_err_int_ena = BIT(NIX_CQERRINT_CQE_FAULT);
aq->cq.cq_err_int_ena |= BIT(NIX_CQERRINT_DOOR_ERR);
+ /* TX pause frames enable flowctrl on RX side */
+ if (dev->fc_info.tx_pause) {
+ /* Single bpid is allocated for all rx channels for now */
+ aq->cq.bpid = dev->fc_info.bpid[0];
+ aq->cq.bp = NIX_CQ_BP_LEVEL;
+ aq->cq.bp_ena = 1;
+ }
+
/* Many to one reduction */
aq->cq.qint_idx = qid % dev->qints;
+ /* Map CQ0 [RQ0] to CINT0 and so on till max 64 irqs */
+ aq->cq.cint_idx = qid;
if (otx2_ethdev_fixup_is_limit_cq_full(dev)) {
uint16_t min_rx_drop;
return rc;
}
+static int
+nix_rq_enb_dis(struct rte_eth_dev *eth_dev,
+ struct otx2_eth_rxq *rxq, const bool enb)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ struct otx2_mbox *mbox = dev->mbox;
+ struct nix_aq_enq_req *aq;
+
+ /* Pkts will be dropped silently if RQ is disabled */
+ aq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
+ aq->qidx = rxq->rq;
+ aq->ctype = NIX_AQ_CTYPE_RQ;
+ aq->op = NIX_AQ_INSTOP_WRITE;
+
+ aq->rq.ena = enb;
+ aq->rq_mask.ena = ~(aq->rq_mask.ena);
+
+ return otx2_mbox_process(mbox);
+}
+
static int
nix_cq_rq_uninit(struct rte_eth_dev *eth_dev, struct otx2_eth_rxq *rxq)
{
static inline int
nix_get_data_off(struct otx2_eth_dev *dev)
{
- RTE_SET_USED(dev);
-
- return 0;
+ return otx2_ethdev_is_ptp_en(dev) ? NIX_TIMESYNC_RX_OFFSET : 0;
}
uint64_t
rxq->pool = mp;
rxq->qlen = nix_qsize_to_val(qsize);
rxq->qsize = qsize;
+ rxq->lookup_mem = otx2_nix_fastpath_lookup_mem_get();
+ rxq->tstamp = &dev->tstamp;
/* Alloc completion queue */
rc = nix_cq_rq_init(eth_dev, dev, rq, rxq, mp);
return NIX_MAXSQESZ_W8;
}
+static uint16_t
+nix_rx_offload_flags(struct rte_eth_dev *eth_dev)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct rte_eth_conf *conf = &data->dev_conf;
+ struct rte_eth_rxmode *rxmode = &conf->rxmode;
+ uint16_t flags = 0;
+
+ if (rxmode->mq_mode == ETH_MQ_RX_RSS)
+ flags |= NIX_RX_OFFLOAD_RSS_F;
+
+ if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
+ DEV_RX_OFFLOAD_UDP_CKSUM))
+ flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
+
+ if (dev->rx_offloads & (DEV_RX_OFFLOAD_IPV4_CKSUM |
+ DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM))
+ flags |= NIX_RX_OFFLOAD_CHECKSUM_F;
+
+ if (dev->rx_offloads & DEV_RX_OFFLOAD_SCATTER)
+ flags |= NIX_RX_MULTI_SEG_F;
+
+ if (dev->rx_offloads & (DEV_RX_OFFLOAD_VLAN_STRIP |
+ DEV_RX_OFFLOAD_QINQ_STRIP))
+ flags |= NIX_RX_OFFLOAD_VLAN_STRIP_F;
+
+ if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
+ flags |= NIX_RX_OFFLOAD_TSTAMP_F;
+
+ return flags;
+}
+
+static uint16_t
+nix_tx_offload_flags(struct rte_eth_dev *eth_dev)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ uint64_t conf = dev->tx_offloads;
+ uint16_t flags = 0;
+
+ /* Fastpath is dependent on these enums */
+ RTE_BUILD_BUG_ON(PKT_TX_TCP_CKSUM != (1ULL << 52));
+ RTE_BUILD_BUG_ON(PKT_TX_SCTP_CKSUM != (2ULL << 52));
+ RTE_BUILD_BUG_ON(PKT_TX_UDP_CKSUM != (3ULL << 52));
+ RTE_BUILD_BUG_ON(PKT_TX_IP_CKSUM != (1ULL << 54));
+ RTE_BUILD_BUG_ON(PKT_TX_IPV4 != (1ULL << 55));
+ RTE_BUILD_BUG_ON(PKT_TX_OUTER_IP_CKSUM != (1ULL << 58));
+ RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV4 != (1ULL << 59));
+ RTE_BUILD_BUG_ON(PKT_TX_OUTER_IPV6 != (1ULL << 60));
+ RTE_BUILD_BUG_ON(PKT_TX_OUTER_UDP_CKSUM != (1ULL << 41));
+ RTE_BUILD_BUG_ON(RTE_MBUF_L2_LEN_BITS != 7);
+ RTE_BUILD_BUG_ON(RTE_MBUF_L3_LEN_BITS != 9);
+ RTE_BUILD_BUG_ON(RTE_MBUF_OUTL2_LEN_BITS != 7);
+ RTE_BUILD_BUG_ON(RTE_MBUF_OUTL3_LEN_BITS != 9);
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) !=
+ offsetof(struct rte_mbuf, buf_iova) + 8);
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
+ offsetof(struct rte_mbuf, buf_iova) + 16);
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
+ offsetof(struct rte_mbuf, ol_flags) + 12);
+ RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, tx_offload) !=
+ offsetof(struct rte_mbuf, pool) + 2 * sizeof(void *));
+
+ if (conf & DEV_TX_OFFLOAD_VLAN_INSERT ||
+ conf & DEV_TX_OFFLOAD_QINQ_INSERT)
+ flags |= NIX_TX_OFFLOAD_VLAN_QINQ_F;
+
+ if (conf & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM ||
+ conf & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM)
+ flags |= NIX_TX_OFFLOAD_OL3_OL4_CSUM_F;
+
+ if (conf & DEV_TX_OFFLOAD_IPV4_CKSUM ||
+ conf & DEV_TX_OFFLOAD_TCP_CKSUM ||
+ conf & DEV_TX_OFFLOAD_UDP_CKSUM ||
+ conf & DEV_TX_OFFLOAD_SCTP_CKSUM)
+ flags |= NIX_TX_OFFLOAD_L3_L4_CSUM_F;
+
+ if (!(conf & DEV_TX_OFFLOAD_MBUF_FAST_FREE))
+ flags |= NIX_TX_OFFLOAD_MBUF_NOFF_F;
+
+ if (conf & DEV_TX_OFFLOAD_MULTI_SEGS)
+ flags |= NIX_TX_MULTI_SEG_F;
+
+ if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP))
+ flags |= NIX_TX_OFFLOAD_TSTAMP_F;
+
+ return flags;
+}
+
static int
nix_sq_init(struct otx2_eth_txq *txq)
{
struct otx2_eth_dev *dev = txq->dev;
struct otx2_mbox *mbox = dev->mbox;
struct nix_aq_enq_req *sq;
+ uint32_t rr_quantum;
+ uint16_t smq;
+ int rc;
if (txq->sqb_pool->pool_id == 0)
return -EINVAL;
+ rc = otx2_nix_tm_get_leaf_data(dev, txq->sq, &rr_quantum, &smq);
+ if (rc) {
+ otx2_err("Failed to get sq->smq(leaf node), rc=%d", rc);
+ return rc;
+ }
+
sq = otx2_mbox_alloc_msg_nix_aq_enq(mbox);
sq->qidx = txq->sq;
sq->ctype = NIX_AQ_CTYPE_SQ;
sq->op = NIX_AQ_INSTOP_INIT;
sq->sq.max_sqe_size = nix_sq_max_sqe_sz(txq);
+ sq->sq.smq = smq;
+ sq->sq.smq_rr_quantum = rr_quantum;
sq->sq.default_chan = dev->tx_chan_base;
sq->sq.sqe_stype = NIX_STYPE_STF;
sq->sq.ena = 1;
send_mem->dsz = 0x0;
send_mem->wmem = 0x1;
send_mem->alg = NIX_SENDMEMALG_SETTSTMP;
+ send_mem->addr = txq->dev->tstamp.tx_tstamp_iova;
}
sg = (union nix_send_sg_s *)&txq->cmd[4];
} else {
otx2_nix_tx_queue_release(void *_txq)
{
struct otx2_eth_txq *txq = _txq;
+ struct rte_eth_dev *eth_dev;
if (!txq)
return;
+ eth_dev = txq->dev->eth_dev;
+
otx2_nix_dbg("Releasing txq %u", txq->sq);
+ /* Flush and disable tm */
+ otx2_nix_tm_sw_xoff(txq, eth_dev->data->dev_started);
+
/* Free sqb's and disable sq */
nix_sq_uninit(txq);
/* Sanity checks */
if (rte_eal_has_hugepages() == 0) {
otx2_err("Huge page is not configured");
- goto fail;
- }
-
- if (rte_eal_iova_mode() != RTE_IOVA_VA) {
- otx2_err("iova mode should be va");
- goto fail;
+ goto fail_configure;
}
if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
otx2_err("Setting link speed/duplex not supported");
- goto fail;
+ goto fail_configure;
}
if (conf->dcb_capability_en == 1) {
otx2_err("dcb enable is not supported");
- goto fail;
+ goto fail_configure;
}
if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
otx2_err("Flow director is not supported");
- goto fail;
+ goto fail_configure;
}
if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
rxmode->mq_mode != ETH_MQ_RX_RSS) {
otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
- goto fail;
+ goto fail_configure;
}
if (txmode->mq_mode != ETH_MQ_TX_NONE) {
otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
- goto fail;
+ goto fail_configure;
+ }
+
+ if (otx2_dev_is_Ax(dev) &&
+ (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
+ ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
+ (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
+ otx2_err("Outer IP and SCTP checksum unsupported");
+ goto fail_configure;
}
/* Free the resources allocated from the previous configure */
if (dev->configured == 1) {
+ otx2_nix_rxchan_bpid_cfg(eth_dev, false);
+ otx2_nix_vlan_fini(eth_dev);
+ otx2_flow_free_all_resources(dev);
oxt2_nix_unregister_queue_irqs(eth_dev);
+ if (eth_dev->data->dev_conf.intr_conf.rxq)
+ oxt2_nix_unregister_cq_irqs(eth_dev);
nix_set_nop_rxtx_function(eth_dev);
rc = nix_store_queue_cfg_and_then_release(eth_dev);
if (rc)
- goto fail;
+ goto fail_configure;
+ otx2_nix_tm_fini(eth_dev);
nix_lf_free(dev);
}
- if (otx2_dev_is_A0(dev) &&
- (txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
- ((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
- (txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
- otx2_err("Outer IP and SCTP checksum unsupported");
- rc = -EINVAL;
- goto fail;
- }
-
dev->rx_offloads = rxmode->offloads;
dev->tx_offloads = txmode->offloads;
+ dev->rx_offload_flags |= nix_rx_offload_flags(eth_dev);
+ dev->tx_offload_flags |= nix_tx_offload_flags(eth_dev);
dev->rss_info.rss_grps = NIX_RSS_GRPS;
nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
if (rc) {
otx2_err("Failed to init nix_lf rc=%d", rc);
- goto fail;
+ goto fail_offloads;
}
/* Configure RSS */
goto free_nix_lf;
}
+ /* Init the default TM scheduler hierarchy */
+ rc = otx2_nix_tm_init_default(eth_dev);
+ if (rc) {
+ otx2_err("Failed to init traffic manager rc=%d", rc);
+ goto free_nix_lf;
+ }
+
+ rc = otx2_nix_vlan_offload_init(eth_dev);
+ if (rc) {
+ otx2_err("Failed to init vlan offload rc=%d", rc);
+ goto tm_fini;
+ }
+
/* Register queue IRQs */
rc = oxt2_nix_register_queue_irqs(eth_dev);
if (rc) {
otx2_err("Failed to register queue interrupts rc=%d", rc);
- goto free_nix_lf;
+ goto vlan_fini;
+ }
+
+ /* Register cq IRQs */
+ if (eth_dev->data->dev_conf.intr_conf.rxq) {
+ if (eth_dev->data->nb_rx_queues > dev->cints) {
+ otx2_err("Rx interrupt cannot be enabled, rxq > %d",
+ dev->cints);
+ goto q_irq_fini;
+ }
+ /* Rx interrupt feature cannot work with vector mode because,
+ * vector mode doesn't process packets unless min 4 pkts are
+ * received, while cq interrupts are generated even for 1 pkt
+ * in the CQ.
+ */
+ dev->scalar_ena = true;
+
+ rc = oxt2_nix_register_cq_irqs(eth_dev);
+ if (rc) {
+ otx2_err("Failed to register CQ interrupts rc=%d", rc);
+ goto q_irq_fini;
+ }
+ }
+
+ /* Configure loop back mode */
+ rc = cgx_intlbk_enable(dev, eth_dev->data->dev_conf.lpbk_mode);
+ if (rc) {
+ otx2_err("Failed to configure cgx loop back mode rc=%d", rc);
+ goto q_irq_fini;
+ }
+
+ rc = otx2_nix_rxchan_bpid_cfg(eth_dev, true);
+ if (rc) {
+ otx2_err("Failed to configure nix rx chan bpid cfg rc=%d", rc);
+ goto q_irq_fini;
}
/*
if (dev->configured == 1) {
rc = nix_restore_queue_cfg(eth_dev);
if (rc)
- goto free_nix_lf;
+ goto cq_fini;
}
/* Update the mac address */
dev->configured_nb_tx_qs = data->nb_tx_queues;
return 0;
+cq_fini:
+ oxt2_nix_unregister_cq_irqs(eth_dev);
+q_irq_fini:
+ oxt2_nix_unregister_queue_irqs(eth_dev);
+vlan_fini:
+ otx2_nix_vlan_fini(eth_dev);
+tm_fini:
+ otx2_nix_tm_fini(eth_dev);
free_nix_lf:
- rc = nix_lf_free(dev);
-fail:
+ nix_lf_free(dev);
+fail_offloads:
+ dev->rx_offload_flags &= ~nix_rx_offload_flags(eth_dev);
+ dev->tx_offload_flags &= ~nix_tx_offload_flags(eth_dev);
+fail_configure:
+ dev->configured = 0;
+ return rc;
+}
+
+int
+otx2_nix_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
+{
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct otx2_eth_txq *txq;
+ int rc = -EINVAL;
+
+ txq = eth_dev->data->tx_queues[qidx];
+
+ if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
+ return 0;
+
+ rc = otx2_nix_sq_sqb_aura_fc(txq, true);
+ if (rc) {
+ otx2_err("Failed to enable sqb aura fc, txq=%u, rc=%d",
+ qidx, rc);
+ goto done;
+ }
+
+ data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
+
+done:
+ return rc;
+}
+
+int
+otx2_nix_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
+{
+ struct rte_eth_dev_data *data = eth_dev->data;
+ struct otx2_eth_txq *txq;
+ int rc;
+
+ txq = eth_dev->data->tx_queues[qidx];
+
+ if (data->tx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
+ return 0;
+
+ txq->fc_cache_pkts = 0;
+
+ rc = otx2_nix_sq_sqb_aura_fc(txq, false);
+ if (rc) {
+ otx2_err("Failed to disable sqb aura fc, txq=%u, rc=%d",
+ qidx, rc);
+ goto done;
+ }
+
+ data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
+
+done:
+ return rc;
+}
+
+static int
+otx2_nix_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t qidx)
+{
+ struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
+ struct rte_eth_dev_data *data = eth_dev->data;
+ int rc;
+
+ if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STARTED)
+ return 0;
+
+ rc = nix_rq_enb_dis(rxq->eth_dev, rxq, true);
+ if (rc) {
+ otx2_err("Failed to enable rxq=%u, rc=%d", qidx, rc);
+ goto done;
+ }
+
+ data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STARTED;
+
+done:
+ return rc;
+}
+
+static int
+otx2_nix_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t qidx)
+{
+ struct otx2_eth_rxq *rxq = eth_dev->data->rx_queues[qidx];
+ struct rte_eth_dev_data *data = eth_dev->data;
+ int rc;
+
+ if (data->rx_queue_state[qidx] == RTE_ETH_QUEUE_STATE_STOPPED)
+ return 0;
+
+ rc = nix_rq_enb_dis(rxq->eth_dev, rxq, false);
+ if (rc) {
+ otx2_err("Failed to disable rxq=%u, rc=%d", qidx, rc);
+ goto done;
+ }
+
+ data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
+
+done:
return rc;
}
+static void
+otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ struct rte_mbuf *rx_pkts[32];
+ struct otx2_eth_rxq *rxq;
+ int count, i, j, rc;
+
+ nix_cgx_stop_link_event(dev);
+ npc_rx_disable(dev);
+
+ /* Stop rx queues and free up pkts pending */
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ rc = otx2_nix_rx_queue_stop(eth_dev, i);
+ if (rc)
+ continue;
+
+ rxq = eth_dev->data->rx_queues[i];
+ count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
+ while (count) {
+ for (j = 0; j < count; j++)
+ rte_pktmbuf_free(rx_pkts[j]);
+ count = dev->rx_pkt_burst_no_offload(rxq, rx_pkts, 32);
+ }
+ }
+
+ /* Stop tx queues */
+ for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
+ otx2_nix_tx_queue_stop(eth_dev, i);
+}
+
+static int
+otx2_nix_dev_start(struct rte_eth_dev *eth_dev)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+ int rc, i;
+
+ if (eth_dev->data->nb_rx_queues != 0) {
+ rc = otx2_nix_recalc_mtu(eth_dev);
+ if (rc)
+ return rc;
+ }
+
+ /* Start rx queues */
+ for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
+ rc = otx2_nix_rx_queue_start(eth_dev, i);
+ if (rc)
+ return rc;
+ }
+
+ /* Start tx queues */
+ for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
+ rc = otx2_nix_tx_queue_start(eth_dev, i);
+ if (rc)
+ return rc;
+ }
+
+ rc = otx2_nix_update_flow_ctrl_mode(eth_dev);
+ if (rc) {
+ otx2_err("Failed to update flow ctrl mode %d", rc);
+ return rc;
+ }
+
+ /* Enable PTP if it was requested by the app or if it is already
+ * enabled in PF owning this VF
+ */
+ memset(&dev->tstamp, 0, sizeof(struct otx2_timesync_info));
+ if ((dev->rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) ||
+ otx2_ethdev_is_ptp_en(dev))
+ otx2_nix_timesync_enable(eth_dev);
+ else
+ otx2_nix_timesync_disable(eth_dev);
+
+ rc = npc_rx_enable(dev);
+ if (rc) {
+ otx2_err("Failed to enable NPC rx %d", rc);
+ return rc;
+ }
+
+ otx2_nix_toggle_flag_link_cfg(dev, true);
+
+ rc = nix_cgx_start_link_event(dev);
+ if (rc) {
+ otx2_err("Failed to start cgx link event %d", rc);
+ goto rx_disable;
+ }
+
+ otx2_nix_toggle_flag_link_cfg(dev, false);
+ otx2_eth_set_tx_function(eth_dev);
+ otx2_eth_set_rx_function(eth_dev);
+
+ return 0;
+
+rx_disable:
+ npc_rx_disable(dev);
+ otx2_nix_toggle_flag_link_cfg(dev, false);
+ return rc;
+}
+
+static int otx2_nix_dev_reset(struct rte_eth_dev *eth_dev);
+static void otx2_nix_dev_close(struct rte_eth_dev *eth_dev);
+
/* Initialize and register driver with DPDK Application */
static const struct eth_dev_ops otx2_eth_dev_ops = {
.dev_infos_get = otx2_nix_info_get,
.tx_queue_release = otx2_nix_tx_queue_release,
.rx_queue_setup = otx2_nix_rx_queue_setup,
.rx_queue_release = otx2_nix_rx_queue_release,
+ .dev_start = otx2_nix_dev_start,
+ .dev_stop = otx2_nix_dev_stop,
+ .dev_close = otx2_nix_dev_close,
+ .tx_queue_start = otx2_nix_tx_queue_start,
+ .tx_queue_stop = otx2_nix_tx_queue_stop,
+ .rx_queue_start = otx2_nix_rx_queue_start,
+ .rx_queue_stop = otx2_nix_rx_queue_stop,
+ .dev_set_link_up = otx2_nix_dev_set_link_up,
+ .dev_set_link_down = otx2_nix_dev_set_link_down,
+ .dev_supported_ptypes_get = otx2_nix_supported_ptypes_get,
+ .dev_reset = otx2_nix_dev_reset,
.stats_get = otx2_nix_dev_stats_get,
.stats_reset = otx2_nix_dev_stats_reset,
.get_reg = otx2_nix_dev_get_reg,
+ .mtu_set = otx2_nix_mtu_set,
.mac_addr_add = otx2_nix_mac_addr_add,
.mac_addr_remove = otx2_nix_mac_addr_del,
.mac_addr_set = otx2_nix_mac_addr_set,
.xstats_reset = otx2_nix_xstats_reset,
.xstats_get_by_id = otx2_nix_xstats_get_by_id,
.xstats_get_names_by_id = otx2_nix_xstats_get_names_by_id,
+ .rxq_info_get = otx2_nix_rxq_info_get,
+ .txq_info_get = otx2_nix_txq_info_get,
+ .rx_queue_count = otx2_nix_rx_queue_count,
+ .rx_descriptor_done = otx2_nix_rx_descriptor_done,
+ .rx_descriptor_status = otx2_nix_rx_descriptor_status,
+ .tx_done_cleanup = otx2_nix_tx_done_cleanup,
+ .pool_ops_supported = otx2_nix_pool_ops_supported,
+ .filter_ctrl = otx2_nix_dev_filter_ctrl,
+ .get_module_info = otx2_nix_get_module_info,
+ .get_module_eeprom = otx2_nix_get_module_eeprom,
+ .fw_version_get = otx2_nix_fw_version_get,
+ .flow_ctrl_get = otx2_nix_flow_ctrl_get,
+ .flow_ctrl_set = otx2_nix_flow_ctrl_set,
+ .timesync_enable = otx2_nix_timesync_enable,
+ .timesync_disable = otx2_nix_timesync_disable,
+ .timesync_read_rx_timestamp = otx2_nix_timesync_read_rx_timestamp,
+ .timesync_read_tx_timestamp = otx2_nix_timesync_read_tx_timestamp,
+ .timesync_adjust_time = otx2_nix_timesync_adjust_time,
+ .timesync_read_time = otx2_nix_timesync_read_time,
+ .timesync_write_time = otx2_nix_timesync_write_time,
+ .vlan_offload_set = otx2_nix_vlan_offload_set,
+ .vlan_filter_set = otx2_nix_vlan_filter_set,
+ .vlan_strip_queue_set = otx2_nix_vlan_strip_queue_set,
+ .vlan_tpid_set = otx2_nix_vlan_tpid_set,
+ .vlan_pvid_set = otx2_nix_vlan_pvid_set,
+ .rx_queue_intr_enable = otx2_nix_rx_queue_intr_enable,
+ .rx_queue_intr_disable = otx2_nix_rx_queue_intr_disable,
};
static inline int
/* Also sync same MAC address to CGX table */
otx2_cgx_mac_addr_set(eth_dev, ð_dev->data->mac_addrs[0]);
+ /* Initialize the tm data structures */
+ otx2_nix_tm_conf_init(eth_dev);
+
dev->tx_offload_capa = nix_get_tx_offload_capa(dev);
dev->rx_offload_capa = nix_get_rx_offload_capa(dev);
- if (otx2_dev_is_A0(dev)) {
+ if (otx2_dev_is_Ax(dev)) {
dev->hwcap |= OTX2_FIXUP_F_MIN_4K_Q;
dev->hwcap |= OTX2_FIXUP_F_LIMIT_CQ_FULL;
}
+ /* Initialize rte-flow */
+ rc = otx2_flow_init(dev);
+ if (rc)
+ goto free_mac_addrs;
+
otx2_nix_dbg("Port=%d pf=%d vf=%d ver=%s msix_off=%d hwcap=0x%" PRIx64
" rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
eth_dev->data->port_id, dev->pf, dev->vf,
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return 0;
+ /* Clear the flag since we are closing down */
+ dev->configured = 0;
+
+ /* Disable nix bpid config */
+ otx2_nix_rxchan_bpid_cfg(eth_dev, false);
+
+ npc_rx_disable(dev);
+
+ /* Disable vlan offloads */
+ otx2_nix_vlan_fini(eth_dev);
+
+ /* Disable other rte_flow entries */
+ otx2_flow_fini(dev);
+
+ /* Disable PTP if already enabled */
+ if (otx2_ethdev_is_ptp_en(dev))
+ otx2_nix_timesync_disable(eth_dev);
+
+ nix_cgx_stop_link_event(dev);
+
/* Free up SQs */
for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
otx2_nix_tx_queue_release(eth_dev->data->tx_queues[i]);
}
eth_dev->data->nb_rx_queues = 0;
+ /* Free tm resources */
+ rc = otx2_nix_tm_fini(eth_dev);
+ if (rc)
+ otx2_err("Failed to cleanup tm, rc=%d", rc);
+
/* Unregister queue irqs */
oxt2_nix_unregister_queue_irqs(eth_dev);
+ /* Unregister cq irqs */
+ if (eth_dev->data->dev_conf.intr_conf.rxq)
+ oxt2_nix_unregister_cq_irqs(eth_dev);
+
rc = nix_lf_free(dev);
if (rc)
otx2_err("Failed to free nix lf, rc=%d", rc);
return 0;
}
+static void
+otx2_nix_dev_close(struct rte_eth_dev *eth_dev)
+{
+ otx2_eth_dev_uninit(eth_dev, true);
+}
+
+static int
+otx2_nix_dev_reset(struct rte_eth_dev *eth_dev)
+{
+ int rc;
+
+ rc = otx2_eth_dev_uninit(eth_dev, false);
+ if (rc)
+ return rc;
+
+ return otx2_eth_dev_init(eth_dev);
+}
+
static int
nix_remove(struct rte_pci_device *pci_dev)
{
static struct rte_pci_driver pci_nix = {
.id_table = pci_nix_map,
- .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA |
+ .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA |
RTE_PCI_DRV_INTR_LSC,
.probe = nix_probe,
.remove = nix_remove,
git.droids-corp.org / dpdk.git / blobdiff