#include <inttypes.h>
-#include <rte_ethdev_pci.h>
+#include <ethdev_pci.h>
#include <rte_io.h>
#include <rte_malloc.h>
#include <rte_mbuf.h>
if (dev->npc_flow.switch_header_type == 0)
return 0;
- if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_LEN_90B &&
- !otx2_dev_is_sdp(dev)) {
- otx2_err("chlen90b is not supported on non-SDP device");
- return -EINVAL;
- }
-
/* Notify AF about higig2 config */
req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
req->mode = dev->npc_flow.switch_header_type;
+ if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_CHLEN90B_PKIND;
+ } else if (dev->npc_flow.switch_header_type ==
+ OTX2_PRIV_FLAGS_CH_LEN_24B) {
+ req->mode = OTX2_PRIV_FLAGS_CUSTOM;
+ req->pkind = NPC_RX_CHLEN24B_PKIND;
+ }
+
if (enable == 0)
req->mode = OTX2_PRIV_FLAGS_DEFAULT;
req->dir = PKIND_RX;
return rc;
req = otx2_mbox_alloc_msg_npc_set_pkind(mbox);
req->mode = dev->npc_flow.switch_header_type;
+ if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_90B ||
+ dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_CH_LEN_24B)
+ req->mode = OTX2_PRIV_FLAGS_DEFAULT;
+
if (enable == 0)
req->mode = OTX2_PRIV_FLAGS_DEFAULT;
req->dir = PKIND_TX;
return 0;
fail:
- if (tx_qconf)
- free(tx_qconf);
- if (rx_qconf)
- free(rx_qconf);
+ free(tx_qconf);
+ free(rx_qconf);
return -ENOMEM;
}
return rc;
}
-static void
+static int
otx2_nix_dev_stop(struct rte_eth_dev *eth_dev)
{
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
/* Stop tx queues */
for (i = 0; i < eth_dev->data->nb_tx_queues; i++)
otx2_nix_tx_queue_stop(eth_dev, i);
+
+ return 0;
}
static int
if (otx2_ethdev_is_ptp_en(dev) && otx2_dev_is_vf(dev))
otx2_nix_ptp_enable_vf(eth_dev);
+ if (dev->rx_offload_flags & NIX_RX_OFFLOAD_TSTAMP_F) {
+ rc = rte_mbuf_dyn_rx_timestamp_register(
+ &dev->tstamp.tstamp_dynfield_offset,
+ &dev->tstamp.rx_tstamp_dynflag);
+ if (rc != 0) {
+ otx2_err("Failed to register Rx timestamp field/flag");
+ return -rte_errno;
+ }
+ }
+
rc = npc_rx_enable(dev);
if (rc) {
otx2_err("Failed to enable NPC rx %d", rc);
pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
rte_eth_copy_pci_info(eth_dev, pci_dev);
+ eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
/* Zero out everything after OTX2_DEV to allow proper dev_reset() */
memset(&dev->otx2_eth_dev_data_start, 0, sizeof(*dev) -