/* Additional timesync values. */
#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
+#define OCTEONTX2_PMD net_octeontx2
+
+#define otx2_ethdev_is_same_driver(dev) \
+ (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
+
enum nix_q_size_e {
nix_q_size_16, /* 16 entries */
nix_q_size_64, /* 64 entries */
nix_q_size_max
};
+enum nix_lso_tun_type {
+ NIX_LSO_TUN_V4V4,
+ NIX_LSO_TUN_V4V6,
+ NIX_LSO_TUN_V6V4,
+ NIX_LSO_TUN_V6V6,
+ NIX_LSO_TUN_MAX,
+};
+
struct otx2_qint {
struct rte_eth_dev *eth_dev;
uint8_t qintx;
uint8_t tx_chan_cnt;
uint8_t lso_tsov4_idx;
uint8_t lso_tsov6_idx;
- uint8_t lso_base_idx;
+ uint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];
+ uint8_t lso_tun_idx[NIX_LSO_TUN_MAX];
+ uint64_t lso_tun_fmt;
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
uint8_t mkex_pfl_name[MKEX_NAME_LEN];
uint8_t max_mac_entries;
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
+ uint64_t lso_tun_fmt;
RTE_MARKER slow_path_start;
uint16_t nb_sqb_bufs;
uint16_t sq;