ethdev: change device info get callback to return int

[dpdk.git] / drivers / net / octeontx2 / otx2_ethdev.h

diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index 3703acc..5de0a1d 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -5,6 +5,7 @@
 #ifndef __OTX2_ETHDEV_H__
 #define __OTX2_ETHDEV_H__
 
+#include <math.h>
 #include <stdint.h>
 
 #include <rte_common.h>
@@ -65,7 +66,8 @@
        (NIX_MAX_FRS - NIX_L2_OVERHEAD)
 
 #define NIX_MAX_SQB                    512
-#define NIX_MIN_SQB                    32
+#define NIX_DEF_SQB                    16
+#define NIX_MIN_SQB                    8
 #define NIX_SQB_LIST_SPACE             2
 #define NIX_RSS_RETA_SIZE_MAX          256
 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
@@ -79,6 +81,7 @@
 #define NIX_CQ_ALIGN                   512
 #define NIX_SQB_LOWER_THRESH           90
 #define LMT_SLOT_MASK                  0x7f
+#define NIX_RX_DEFAULT_RING_SZ         4096
 
 /* If PTP is enabled additional SEND MEM DESC is required which
  * takes 2 words, hence max 7 iova address are possible
@@ -93,8 +96,9 @@
        ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
         + NIX_TX_NB_SEG_MAX)
 
-/* Apply BP when CQ is 75% full */
-#define NIX_CQ_BP_LEVEL (25 * 256 / 100)
+/* Apply BP/DROP when CQ is 95% full */
+#define NIX_CQ_THRESH_LEVEL    (5 * 256 / 100)
+#define NIX_CQ_FULL_ERRATA_SKID        (1024ull * 256)
 
 #define CQ_OP_STAT_OP_ERR      63
 #define CQ_OP_STAT_CQ_ERR      46
@@ -102,6 +106,13 @@
 #define OP_ERR                 BIT_ULL(CQ_OP_STAT_OP_ERR)
 #define CQ_ERR                 BIT_ULL(CQ_OP_STAT_CQ_ERR)
 
+#define CQ_CQE_THRESH_DEFAULT  0x1ULL /* IRQ triggered when
+                                       * NIX_LF_CINTX_CNT[QCOUNT]
+                                       * crosses this value
+                                       */
+#define CQ_TIMER_THRESH_DEFAULT        0xAULL /* ~1usec i.e (0xA * 100nsec) */
+#define CQ_TIMER_THRESH_MAX     255
+
 #define NIX_RSS_OFFLOAD                (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
                                 ETH_RSS_TCP | ETH_RSS_SCTP | \
                                 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD)
@@ -248,6 +259,7 @@ struct otx2_eth_dev {
        uint16_t qints;
        uint8_t configured;
        uint8_t configured_qints;
+       uint8_t configured_cints;
        uint8_t configured_nb_rx_qs;
        uint8_t configured_nb_tx_qs;
        uint16_t nix_msixoff;
@@ -262,6 +274,7 @@ struct otx2_eth_dev {
        uint64_t rx_offload_capa;
        uint64_t tx_offload_capa;
        struct otx2_qint qints_mem[RTE_MAX_QUEUES_PER_PORT];
+       struct otx2_qint cints_mem[RTE_MAX_QUEUES_PER_PORT];
        uint16_t txschq[NIX_TXSCH_LVL_CNT];
        uint16_t txschq_contig[NIX_TXSCH_LVL_CNT];
        uint16_t txschq_index[NIX_TXSCH_LVL_CNT];
@@ -291,6 +304,8 @@ struct otx2_eth_dev {
        struct rte_timecounter  systime_tc;
        struct rte_timecounter  rx_tstamp_tc;
        struct rte_timecounter  tx_tstamp_tc;
+       double clk_freq_mult;
+       uint64_t clk_delta;
 } __rte_cache_aligned;
 
 struct otx2_eth_txq {
@@ -332,6 +347,7 @@ struct otx2_eth_rxq {
        enum nix_q_size_e qsize;
        struct rte_eth_dev *eth_dev;
        struct otx2_eth_qconf qconf;
+       uint16_t cq_drop;
 } __rte_cache_aligned;
 
 static inline struct otx2_eth_dev *
@@ -341,8 +357,8 @@ otx2_eth_pmd_priv(struct rte_eth_dev *eth_dev)
 }
 
 /* Ops */
-void otx2_nix_info_get(struct rte_eth_dev *eth_dev,
-                      struct rte_eth_dev_info *dev_info);
+int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
+                     struct rte_eth_dev_info *dev_info);
 int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
                             enum rte_filter_type filter_type,
                             enum rte_filter_op filter_op, void *arg);
@@ -380,12 +396,21 @@ void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
 int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
 void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
                                     struct cgx_link_user_info *link);
+int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
+int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
 
 /* IRQ */
 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
 int oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev);
+int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
+void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+
+int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
+                                 uint16_t rx_queue_id);
+int otx2_nix_rx_queue_intr_disable(struct rte_eth_dev *eth_dev,
+                                  uint16_t rx_queue_id);
 
 /* Debug */
 int otx2_nix_reg_dump(struct otx2_eth_dev *dev, uint64_t *data);
@@ -509,5 +534,7 @@ int otx2_nix_timesync_write_time(struct rte_eth_dev *eth_dev,
 int otx2_nix_timesync_read_time(struct rte_eth_dev *eth_dev,
                                struct timespec *ts);
 int otx2_eth_dev_ptp_info_update(struct otx2_dev *dev, bool ptp_en);
+int otx2_nix_read_clock(struct rte_eth_dev *eth_dev, uint64_t *time);
+int otx2_nix_raw_clock_tsc_conv(struct otx2_eth_dev *dev);
 
 #endif /* __OTX2_ETHDEV_H__ */