#include <rte_kvargs.h>
#include <rte_mbuf.h>
#include <rte_mempool.h>
+#include <rte_security_driver.h>
+#include <rte_spinlock.h>
#include <rte_string_fns.h>
#include <rte_time.h>
/* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
#define NIX_L2_OVERHEAD \
(RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
+#define NIX_L2_MAX_LEN \
+ (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
/* HW config of frame size doesn't include FCS */
#define NIX_MAX_HW_FRS 9212
#define NIX_RSS_OFFLOAD (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
ETH_RSS_TCP | ETH_RSS_SCTP | \
ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
- NIX_RSS_L3_L4_SRC_DST)
+ NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
+ ETH_RSS_C_VLAN)
#define NIX_TX_OFFLOAD_CAPA ( \
DEV_TX_OFFLOAD_MBUF_FAST_FREE | \
/* Additional timesync values. */
#define OTX2_CYCLECOUNTER_MASK 0xffffffffffffffffULL
+#define OCTEONTX2_PMD net_octeontx2
+
+#define otx2_ethdev_is_same_driver(dev) \
+ (strcmp((dev)->device->driver->name, RTE_STR(OCTEONTX2_PMD)) == 0)
+
enum nix_q_size_e {
nix_q_size_16, /* 16 entries */
nix_q_size_64, /* 64 entries */
nix_q_size_max
};
+enum nix_lso_tun_type {
+ NIX_LSO_TUN_V4V4,
+ NIX_LSO_TUN_V4V6,
+ NIX_LSO_TUN_V6V4,
+ NIX_LSO_TUN_V6V6,
+ NIX_LSO_TUN_MAX,
+};
+
struct otx2_qint {
struct rte_eth_dev *eth_dev;
uint8_t qintx;
void *mempool;
uint32_t socket_id;
uint16_t nb_desc;
+ uint8_t valid;
};
struct otx2_fc_info {
uint8_t tx_chan_cnt;
uint8_t lso_tsov4_idx;
uint8_t lso_tsov6_idx;
- uint8_t lso_base_idx;
+ uint8_t lso_udp_tun_idx[NIX_LSO_TUN_MAX];
+ uint8_t lso_tun_idx[NIX_LSO_TUN_MAX];
+ uint64_t lso_tun_fmt;
uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
uint8_t mkex_pfl_name[MKEX_NAME_LEN];
uint8_t max_mac_entries;
+ bool dmac_filter_enable;
uint8_t lf_tx_stats;
uint8_t lf_rx_stats;
+ uint8_t lock_rx_ctx;
+ uint8_t lock_tx_ctx;
uint16_t flags;
uint16_t cints;
uint16_t qints;
uint16_t link_cfg_lvl;
uint16_t tm_flags;
uint16_t tm_leaf_cnt;
+ uint64_t tm_rate_min;
struct otx2_nix_tm_node_list node_list;
struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
struct otx2_rss_info rss_info;
bool sdp_link; /* SDP flag */
/* Inline IPsec params */
uint16_t ipsec_in_max_spi;
+ rte_spinlock_t ipsec_tbl_lock;
uint8_t duplex;
uint32_t speed;
} __rte_cache_aligned;
rte_iova_t fc_iova;
uint16_t sqes_per_sqb_log2;
int16_t nb_sqb_bufs_adj;
+ uint64_t lso_tun_fmt;
RTE_MARKER slow_path_start;
uint16_t nb_sqb_bufs;
uint16_t sq;
/* Ops */
int otx2_nix_info_get(struct rte_eth_dev *eth_dev,
struct rte_eth_dev_info *dev_info);
-int otx2_nix_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
- enum rte_filter_type filter_type,
- enum rte_filter_op filter_op, void *arg);
+int otx2_nix_dev_flow_ops_get(struct rte_eth_dev *eth_dev,
+ const struct rte_flow_ops **ops);
int otx2_nix_fw_version_get(struct rte_eth_dev *eth_dev, char *fw_version,
size_t fw_size);
int otx2_nix_get_module_info(struct rte_eth_dev *eth_dev,
/* MTU */
int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
+void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
+
/* Link */
void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
int otx2_nix_link_update(struct rte_eth_dev *eth_dev, int wait_to_complete);
void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
struct cgx_link_user_info *link);
+void otx2_eth_dev_link_status_get(struct otx2_dev *dev,
+ struct cgx_link_user_info *link);
int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
struct rte_dev_reg_info *regs);
int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
+void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
/* Stats */
int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,