net/octeontx2: support 96xx A1 silicon revision

[dpdk.git] / drivers / net / octeontx2 / otx2_ethdev.h

diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index 720386f..7b15d6b 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -66,7 +66,8 @@
        (NIX_MAX_FRS - NIX_L2_OVERHEAD)
 
 #define NIX_MAX_SQB                    512
-#define NIX_MIN_SQB                    32
+#define NIX_DEF_SQB                    16
+#define NIX_MIN_SQB                    8
 #define NIX_SQB_LIST_SPACE             2
 #define NIX_RSS_RETA_SIZE_MAX          256
 /* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
@@ -80,6 +81,7 @@
 #define NIX_CQ_ALIGN                   512
 #define NIX_SQB_LOWER_THRESH           90
 #define LMT_SLOT_MASK                  0x7f
+#define NIX_RX_DEFAULT_RING_SZ         4096
 
 /* If PTP is enabled additional SEND MEM DESC is required which
  * takes 2 words, hence max 7 iova address are possible
@@ -94,8 +96,9 @@
        ((RTE_ALIGN_MUL_CEIL(NIX_TX_NB_SEG_MAX, 3) / 3) \
         + NIX_TX_NB_SEG_MAX)
 
-/* Apply BP when CQ is 75% full */
-#define NIX_CQ_BP_LEVEL (25 * 256 / 100)
+/* Apply BP/DROP when CQ is 95% full */
+#define NIX_CQ_THRESH_LEVEL    (5 * 256 / 100)
+#define NIX_CQ_FULL_ERRATA_SKID        (1024ull * 256)
 
 #define CQ_OP_STAT_OP_ERR      63
 #define CQ_OP_STAT_CQ_ERR      46
@@ -344,6 +347,7 @@ struct otx2_eth_rxq {
        enum nix_q_size_e qsize;
        struct rte_eth_dev *eth_dev;
        struct otx2_eth_qconf qconf;
+       uint16_t cq_drop;
 } __rte_cache_aligned;
 
 static inline struct otx2_eth_dev *