ethdev: make driver-only headers private

[dpdk.git] / drivers / net / octeontx2 / otx2_ethdev.h

diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h
index c075b8d..99f0469 100644 (file)
--- a/drivers/net/octeontx2/otx2_ethdev.h
+++ b/drivers/net/octeontx2/otx2_ethdev.h
@@ -13,6 +13,7 @@
 #include <rte_kvargs.h>
 #include <rte_mbuf.h>
 #include <rte_mempool.h>
+#include <rte_security_driver.h>
 #include <rte_string_fns.h>
 #include <rte_time.h>
 
@@ -50,6 +51,8 @@
 /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */
 #define NIX_L2_OVERHEAD \
        (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 8)
+#define NIX_L2_MAX_LEN \
+       (RTE_ETHER_MTU + NIX_L2_OVERHEAD)
 
 /* HW config of frame size doesn't include FCS */
 #define NIX_MAX_HW_FRS                 9212
@@ -119,7 +122,8 @@
 #define NIX_RSS_OFFLOAD                (ETH_RSS_PORT | ETH_RSS_IP | ETH_RSS_UDP |\
                                 ETH_RSS_TCP | ETH_RSS_SCTP | \
                                 ETH_RSS_TUNNEL | ETH_RSS_L2_PAYLOAD | \
-                                NIX_RSS_L3_L4_SRC_DST)
+                                NIX_RSS_L3_L4_SRC_DST | ETH_RSS_LEVEL_MASK | \
+                                ETH_RSS_C_VLAN)
 
 #define NIX_TX_OFFLOAD_CAPA ( \
        DEV_TX_OFFLOAD_MBUF_FAST_FREE   | \
@@ -196,6 +200,7 @@ struct otx2_eth_qconf {
        void *mempool;
        uint32_t socket_id;
        uint16_t nb_desc;
+       uint8_t valid;
 };
 
 struct otx2_fc_info {
@@ -270,8 +275,11 @@ struct otx2_eth_dev {
        uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
        uint8_t mkex_pfl_name[MKEX_NAME_LEN];
        uint8_t max_mac_entries;
+       bool dmac_filter_enable;
        uint8_t lf_tx_stats;
        uint8_t lf_rx_stats;
+       uint8_t lock_rx_ctx;
+       uint8_t lock_tx_ctx;
        uint16_t flags;
        uint16_t cints;
        uint16_t qints;
@@ -285,6 +293,7 @@ struct otx2_eth_dev {
        uintptr_t base;
        uintptr_t lmt_addr;
        uint16_t scalar_ena;
+       uint16_t rss_tag_as_xor;
        uint16_t max_sqb_count;
        uint16_t rx_offload_flags; /* Selected Rx offload flags(NIX_RX_*_F) */
        uint64_t rx_offloads;
@@ -303,8 +312,10 @@ struct otx2_eth_dev {
        /* Contiguous queues */
        uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
        uint16_t otx2_tm_root_lvl;
+       uint16_t link_cfg_lvl;
        uint16_t tm_flags;
        uint16_t tm_leaf_cnt;
+       uint64_t tm_rate_min;
        struct otx2_nix_tm_node_list node_list;
        struct otx2_nix_tm_shaper_profile_list shaper_profile_list;
        struct otx2_rss_info rss_info;
@@ -328,6 +339,10 @@ struct otx2_eth_dev {
        bool mc_tbl_set;
        struct otx2_nix_mc_filter_tbl mc_fltr_tbl;
        bool sdp_link; /* SDP flag */
+       /* Inline IPsec params */
+       uint16_t ipsec_in_max_spi;
+       uint8_t duplex;
+       uint32_t speed;
 } __rte_cache_aligned;
 
 struct otx2_eth_txq {
@@ -426,6 +441,8 @@ int otx2_nix_set_mc_addr_list(struct rte_eth_dev *eth_dev,
 /* MTU */
 int otx2_nix_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu);
 int otx2_nix_recalc_mtu(struct rte_eth_dev *eth_dev);
+void otx2_nix_enable_mseg_on_jumbo(struct otx2_eth_rxq *rxq);
+
 
 /* Link */
 void otx2_nix_toggle_flag_link_cfg(struct otx2_eth_dev *dev, bool set);
@@ -434,6 +451,7 @@ void otx2_eth_dev_link_status_update(struct otx2_dev *dev,
                                     struct cgx_link_user_info *link);
 int otx2_nix_dev_set_link_up(struct rte_eth_dev *eth_dev);
 int otx2_nix_dev_set_link_down(struct rte_eth_dev *eth_dev);
+int otx2_apply_link_speed(struct rte_eth_dev *eth_dev);
 
 /* IRQ */
 int otx2_nix_register_irqs(struct rte_eth_dev *eth_dev);
@@ -442,6 +460,8 @@ int oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev);
 void otx2_nix_unregister_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev);
 void oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev);
+void otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
+void otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb);
 
 int otx2_nix_rx_queue_intr_enable(struct rte_eth_dev *eth_dev,
                                  uint16_t rx_queue_id);
@@ -454,6 +474,7 @@ int otx2_nix_dev_get_reg(struct rte_eth_dev *eth_dev,
                         struct rte_dev_reg_info *regs);
 int otx2_nix_queues_ctx_dump(struct rte_eth_dev *eth_dev);
 void otx2_nix_cqe_dump(const struct nix_cqe_hdr_s *cq);
+void otx2_nix_tm_dump(struct otx2_eth_dev *dev);
 
 /* Stats */
 int otx2_nix_dev_stats_get(struct rte_eth_dev *eth_dev,
@@ -508,6 +529,8 @@ int otx2_cgx_mac_addr_set(struct rte_eth_dev *eth_dev,
                          struct rte_ether_addr *addr);
 
 /* Flow Control */
+int otx2_nix_flow_ctrl_init(struct rte_eth_dev *eth_dev);
+
 int otx2_nix_flow_ctrl_get(struct rte_eth_dev *eth_dev,
                           struct rte_eth_fc_conf *fc_conf);