nix_lf_register_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
- otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+ otx2_nix_err_intr_enb_dis(eth_dev, false);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_err_irq, eth_dev, vec);
/* Enable all dev interrupt except for RQ_DISABLED */
- otx2_write64(~BIT_ULL(11), dev->base + NIX_LF_ERR_INT_ENA_W1S);
+ otx2_nix_err_intr_enb_dis(eth_dev, true);
return rc;
}
nix_lf_unregister_err_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_ERR_INT;
/* Clear err interrupt */
- otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+ otx2_nix_err_intr_enb_dis(eth_dev, false);
otx2_unregister_irq(handle, nix_lf_err_irq, eth_dev, vec);
}
nix_lf_register_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int rc, vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
- otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+ otx2_nix_ras_intr_enb_dis(eth_dev, false);
/* Set used interrupt vectors */
rc = otx2_register_irq(handle, nix_lf_ras_irq, eth_dev, vec);
/* Enable dev interrupt */
- otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+ otx2_nix_ras_intr_enb_dis(eth_dev, true);
return rc;
}
nix_lf_unregister_ras_irq(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec;
vec = dev->nix_msixoff + NIX_LF_INT_VEC_POISON;
/* Clear err interrupt */
- otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+ otx2_nix_ras_intr_enb_dis(eth_dev, false);
otx2_unregister_irq(handle, nix_lf_ras_irq, eth_dev, vec);
}
qint = reg & 0xff;
wdata &= mask;
- otx2_write64(wdata, dev->base + off);
+ otx2_write64(wdata | qint, dev->base + off);
return qint;
}
oxt2_nix_register_queue_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q, sqs, rqs, qs, rc = 0;
oxt2_nix_unregister_queue_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q;
oxt2_nix_register_cq_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
uint8_t rc = 0, vec, q;
return rc;
}
- if (!handle->intr_vec) {
- handle->intr_vec = rte_zmalloc("intr_vec",
- dev->configured_cints *
- sizeof(int), 0);
- if (!handle->intr_vec) {
- otx2_err("Failed to allocate %d rx intr_vec",
- dev->configured_cints);
- return -ENOMEM;
- }
+ rc = rte_intr_vec_list_alloc(handle, "intr_vec",
+ dev->configured_cints);
+ if (rc) {
+ otx2_err("Fail to allocate intr vec list, "
+ "rc=%d", rc);
+ return rc;
}
/* VFIO vector zero is resereved for misc interrupt so
* doing required adjustment. (b13bfab4cd)
*/
- handle->intr_vec[q] = RTE_INTR_VEC_RXTX_OFFSET + vec;
+ if (rte_intr_vec_list_index_set(handle, q,
+ RTE_INTR_VEC_RXTX_OFFSET + vec))
+ return -1;
/* Configure CQE interrupt coalescing parameters */
otx2_write64(((CQ_CQE_THRESH_DEFAULT) |
oxt2_nix_unregister_cq_irqs(struct rte_eth_dev *eth_dev)
{
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
- struct rte_intr_handle *handle = &pci_dev->intr_handle;
+ struct rte_intr_handle *handle = pci_dev->intr_handle;
struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
int vec, q;
return 0;
}
+
+void
+otx2_nix_err_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+ /* Enable all nix lf error interrupts except
+ * RQ_DISABLED and CQ_DISABLED.
+ */
+ if (enb)
+ otx2_write64(~(BIT_ULL(11) | BIT_ULL(24)),
+ dev->base + NIX_LF_ERR_INT_ENA_W1S);
+ else
+ otx2_write64(~0ull, dev->base + NIX_LF_ERR_INT_ENA_W1C);
+}
+
+void
+otx2_nix_ras_intr_enb_dis(struct rte_eth_dev *eth_dev, bool enb)
+{
+ struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
+
+ if (enb)
+ otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1S);
+ else
+ otx2_write64(~0ull, dev->base + NIX_LF_RAS_ENA_W1C);
+}