net/qede: remove flags from Tx entry

[dpdk.git] / drivers / net / octeontx2 / otx2_tm.h

diff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h
index ad7727e..db44d48 100644 (file)
--- a/drivers/net/octeontx2/otx2_tm.h
+++ b/drivers/net/octeontx2/otx2_tm.h
@@ -10,6 +10,8 @@
 #include <rte_tm_driver.h>
 
 #define NIX_TM_DEFAULT_TREE    BIT_ULL(0)
+#define NIX_TM_COMMITTED       BIT_ULL(1)
+#define NIX_TM_RATE_LIMIT_TREE BIT_ULL(2)
 #define NIX_TM_TL1_NO_SP       BIT_ULL(3)
 
 struct otx2_eth_dev;
@@ -17,9 +19,15 @@ struct otx2_eth_dev;
 void otx2_nix_tm_conf_init(struct rte_eth_dev *eth_dev);
 int otx2_nix_tm_init_default(struct rte_eth_dev *eth_dev);
 int otx2_nix_tm_fini(struct rte_eth_dev *eth_dev);
+int otx2_nix_tm_ops_get(struct rte_eth_dev *eth_dev, void *ops);
 int otx2_nix_tm_get_leaf_data(struct otx2_eth_dev *dev, uint16_t sq,
                              uint32_t *rr_quantum, uint16_t *smq);
-int otx2_nix_tm_sw_xoff(void *_txq, bool dev_started);
+int otx2_nix_tm_set_queue_rate_limit(struct rte_eth_dev *eth_dev,
+                                    uint16_t queue_idx, uint16_t tx_rate);
+int otx2_nix_sq_flush_pre(void *_txq, bool dev_started);
+int otx2_nix_sq_flush_post(void *_txq);
+int otx2_nix_sq_enable(void *_txq);
+int otx2_nix_get_link(struct otx2_eth_dev *dev);
 int otx2_nix_sq_sqb_aura_fc(void *_txq, bool enable);
 
 struct otx2_nix_tm_node {
@@ -38,10 +46,17 @@ struct otx2_nix_tm_node {
 #define NIX_TM_NODE_HWRES      BIT_ULL(0)
 #define NIX_TM_NODE_ENABLED    BIT_ULL(1)
 #define NIX_TM_NODE_USER       BIT_ULL(2)
+#define NIX_TM_NODE_RED_DISCARD BIT_ULL(3)
        /* Shaper algorithm for RED state @NIX_REDALG_E */
        uint32_t red_algo:2;
+       uint32_t pkt_mode:1;
+
        struct otx2_nix_tm_node *parent;
        struct rte_tm_node_params params;
+
+       /* Last stats */
+       uint64_t last_pkts;
+       uint64_t last_bytes;
 };
 
 struct otx2_nix_tm_shaper_profile {
@@ -70,7 +85,6 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
                ((((__weight) & MAX_SCHED_WEIGHT) *             \
                  NIX_TM_RR_QUANTUM_MAX) / MAX_SCHED_WEIGHT)
 
-
 /* DEFAULT_RR_WEIGHT * NIX_TM_RR_QUANTUM_MAX / MAX_SCHED_WEIGHT  */
 /* = NIX_MAX_HW_MTU */
 #define DEFAULT_RR_WEIGHT 71
@@ -102,6 +116,10 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
 #define MAX_SHAPER_RATE \
        SHAPER_RATE(MAX_RATE_EXPONENT, MAX_RATE_MANTISSA, 0)
 
+/* Min is limited so that NIX_AF_SMQX_CFG[MINLEN]+ADJUST is not -ve */
+#define NIX_LENGTH_ADJUST_MIN ((int)-NIX_MIN_HW_FRS + 1)
+#define NIX_LENGTH_ADJUST_MAX 255
+
 /** TM Shaper - low level operations */
 
 /** NIX burst limits */
@@ -132,6 +150,8 @@ TAILQ_HEAD(otx2_nix_tm_shaper_profile_list, otx2_nix_tm_shaper_profile);
 #define TXSCH_TL1_DFLT_RR_QTM  ((1 << 24) - 1)
 #define TXSCH_TL1_DFLT_RR_PRIO 1
 
+#define TXSCH_TLX_SP_PRIO_MAX 10
+
 static inline const char *
 nix_hwlvl2str(uint32_t hw_lvl)
 {