* Copyright(C) 2021 Marvell.
*/
-#include "otx2_common.h"
+#include <rte_common.h>
+#include <rte_cycles.h>
#include "otx_ep_common.h"
#include "otx2_ep_vf.h"
iq->inst_cnt_reg = (uint8_t *)otx_ep->hw_addr +
SDP_VF_R_IN_CNTS(iq_no);
- otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p",
+ otx_ep_dbg("InstQ[%d]:dbell reg @ 0x%p inst_cnt_reg @ 0x%p",
iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
do {
rte_read32(droq->pkts_sent_reg));
}
+static int
+otx2_vf_enable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t loop = SDP_VF_BUSY_LOOP_COUNT;
+ uint64_t reg_val = 0ull;
+
+ /* Resetting doorbells during IQ enabling also to handle abrupt
+ * guest reboot. IQ reset does not clear the doorbells.
+ */
+ otx2_write64(0xFFFFFFFF, otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no));
+
+ while (((otx2_read64(otx_ep->hw_addr +
+ SDP_VF_R_IN_INSTR_DBELL(q_no))) != 0ull) && loop--) {
+ rte_delay_ms(1);
+ }
+
+ if (!loop) {
+ otx_ep_err("INSTR DBELL not coming back to 0\n");
+ return -EIO;
+ }
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ reg_val |= 0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+
+ otx_ep_info("IQ[%d] enable done", q_no);
+
+ return 0;
+}
+
+static int
+otx2_vf_enable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+ reg_val |= 0x1ull;
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+
+ otx_ep_info("OQ[%d] enable done", q_no);
+
+ return 0;
+}
+
+static int
+otx2_vf_enable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+ int ret;
+
+ for (q_no = 0; q_no < otx_ep->nb_tx_queues; q_no++) {
+ ret = otx2_vf_enable_iq(otx_ep, q_no);
+ if (ret)
+ return ret;
+ }
+
+ for (q_no = 0; q_no < otx_ep->nb_rx_queues; q_no++)
+ otx2_vf_enable_oq(otx_ep, q_no);
+
+ return 0;
+}
+
+static void
+otx2_vf_disable_iq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ uint64_t reg_val = 0ull;
+
+ /* Reset the doorbell register for this Input Queue. */
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_IN_ENABLE(q_no));
+}
+
+static void
+otx2_vf_disable_oq(struct otx_ep_device *otx_ep, uint32_t q_no)
+{
+ volatile uint64_t reg_val = 0ull;
+
+ reg_val = otx2_read64(otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+ reg_val &= ~0x1ull;
+
+ otx2_write64(reg_val, otx_ep->hw_addr + SDP_VF_R_OUT_ENABLE(q_no));
+}
+
+static void
+otx2_vf_disable_io_queues(struct otx_ep_device *otx_ep)
+{
+ uint32_t q_no = 0;
+
+ for (q_no = 0; q_no < otx_ep->sriov_info.rings_per_vf; q_no++) {
+ otx2_vf_disable_iq(otx_ep, q_no);
+ otx2_vf_disable_oq(otx_ep, q_no);
+ }
+}
+
static const struct otx_ep_config default_otx2_ep_conf = {
/* IQ attributes */
.iq = {
if (otx_ep->conf == NULL) {
otx_ep->conf = otx2_ep_get_defconf(otx_ep);
if (otx_ep->conf == NULL) {
- otx2_err("SDP VF default config not found");
+ otx_ep_err("SDP VF default config not found");
return -ENOENT;
}
- otx2_info("Default config is used");
+ otx_ep_info("Default config is used");
}
/* Get IOQs (RPVF] count */
otx_ep->sriov_info.rings_per_vf = ((reg_val >> SDP_VF_R_IN_CTL_RPVF_POS)
& SDP_VF_R_IN_CTL_RPVF_MASK);
- otx2_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
+ otx_ep_info("SDP RPVF: %d", otx_ep->sriov_info.rings_per_vf);
otx_ep->fn_list.setup_iq_regs = otx2_vf_setup_iq_regs;
otx_ep->fn_list.setup_oq_regs = otx2_vf_setup_oq_regs;
otx_ep->fn_list.setup_device_regs = otx2_vf_setup_device_regs;
+ otx_ep->fn_list.enable_io_queues = otx2_vf_enable_io_queues;
+ otx_ep->fn_list.disable_io_queues = otx2_vf_disable_io_queues;
+
+ otx_ep->fn_list.enable_iq = otx2_vf_enable_iq;
+ otx_ep->fn_list.disable_iq = otx2_vf_disable_iq;
+
+ otx_ep->fn_list.enable_oq = otx2_vf_enable_oq;
+ otx_ep->fn_list.disable_oq = otx2_vf_disable_oq;
+
return 0;
}