net/ice: refine debug build option

[dpdk.git] / drivers / net / octeontx_ep / otx_ep_ethdev.c

diff --git a/drivers/net/octeontx_ep/otx_ep_ethdev.c b/drivers/net/octeontx_ep/otx_ep_ethdev.c
index e936901..b35c88b 100644 (file)
--- a/drivers/net/octeontx_ep/otx_ep_ethdev.c
+++ b/drivers/net/octeontx_ep/otx_ep_ethdev.c
@@ -51,6 +51,46 @@ otx_ep_dev_info_get(struct rte_eth_dev *eth_dev,
        return 0;
 }
 
+static int
+otx_ep_dev_start(struct rte_eth_dev *eth_dev)
+{
+       struct otx_ep_device *otx_epvf;
+       unsigned int q;
+       int ret;
+
+       otx_epvf = (struct otx_ep_device *)OTX_EP_DEV(eth_dev);
+       /* Enable IQ/OQ for this device */
+       ret = otx_epvf->fn_list.enable_io_queues(otx_epvf);
+       if (ret) {
+               otx_ep_err("IOQ enable failed\n");
+               return ret;
+       }
+
+       for (q = 0; q < otx_epvf->nb_rx_queues; q++) {
+               rte_write32(otx_epvf->droq[q]->nb_desc,
+                           otx_epvf->droq[q]->pkts_credit_reg);
+
+               rte_wmb();
+               otx_ep_info("OQ[%d] dbells [%d]\n", q,
+               rte_read32(otx_epvf->droq[q]->pkts_credit_reg));
+       }
+
+       otx_ep_info("dev started\n");
+
+       return 0;
+}
+
+/* Stop device and disable input/output functions */
+static int
+otx_ep_dev_stop(struct rte_eth_dev *eth_dev)
+{
+       struct otx_ep_device *otx_epvf = OTX_EP_DEV(eth_dev);
+
+       otx_epvf->fn_list.disable_io_queues(otx_epvf);
+
+       return 0;
+}
+
 static int
 otx_ep_chip_specific_setup(struct otx_ep_device *otx_epvf)
 {
@@ -96,6 +136,12 @@ otx_epdev_init(struct otx_ep_device *otx_epvf)
 
        otx_epvf->fn_list.setup_device_regs(otx_epvf);
 
+       otx_epvf->eth_dev->rx_pkt_burst = &otx_ep_recv_pkts;
+       if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX_EP_VF)
+               otx_epvf->eth_dev->tx_pkt_burst = &otx_ep_xmit_pkts;
+       else if (otx_epvf->chip_id == PCI_DEVID_OCTEONTX2_EP_NET_VF ||
+                otx_epvf->chip_id == PCI_DEVID_CN98XX_EP_NET_VF)
+               otx_epvf->eth_dev->tx_pkt_burst = &otx2_ep_xmit_pkts;
        ethdev_queues = (uint32_t)(otx_epvf->sriov_info.rings_per_vf);
        otx_epvf->max_rx_queues = ethdev_queues;
        otx_epvf->max_tx_queues = ethdev_queues;
@@ -292,6 +338,8 @@ otx_ep_tx_queue_release(void *txq)
 /* Define our ethernet definitions */
 static const struct eth_dev_ops otx_ep_eth_dev_ops = {
        .dev_configure          = otx_ep_dev_configure,
+       .dev_start              = otx_ep_dev_start,
+       .dev_stop               = otx_ep_dev_stop,
        .rx_queue_setup         = otx_ep_rx_queue_setup,
        .rx_queue_release       = otx_ep_rx_queue_release,
        .tx_queue_setup         = otx_ep_tx_queue_setup,
@@ -309,6 +357,8 @@ otx_epdev_exit(struct rte_eth_dev *eth_dev)
 
        otx_epvf = OTX_EP_DEV(eth_dev);
 
+       otx_epvf->fn_list.disable_io_queues(otx_epvf);
+
        num_queues = otx_epvf->nb_rx_queues;
        for (q = 0; q < num_queues; q++) {
                if (otx_ep_delete_oqs(otx_epvf, q)) {
@@ -338,6 +388,8 @@ otx_ep_eth_dev_uninit(struct rte_eth_dev *eth_dev)
        otx_epdev_exit(eth_dev);
 
        eth_dev->dev_ops = NULL;
+       eth_dev->rx_pkt_burst = NULL;
+       eth_dev->tx_pkt_burst = NULL;
 
        return 0;
 }