net/ice/base: fix abbreviations

[dpdk.git] / drivers / net / qede / base / bcm_osal.c

diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c
index 91017b8..65837b5 100644 (file)
--- a/drivers/net/qede/base/bcm_osal.c
+++ b/drivers/net/qede/base/bcm_osal.c
@@ -1,9 +1,7 @@
-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 #include <rte_memzone.h>
@@ -12,6 +10,7 @@
 #include "bcm_osal.h"
 #include "ecore.h"
 #include "ecore_hw.h"
+#include "ecore_dev_api.h"
 #include "ecore_iov_api.h"
 #include "ecore_mcp_api.h"
 #include "ecore_l2_api.h"
@@ -19,7 +18,7 @@
 /* Array of memzone pointers */
 static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
 /* Counter to track current memzone allocated */
-uint16_t ecore_mz_count;
+static uint16_t ecore_mz_count;
 
 unsigned long qede_log2_align(unsigned long n)
 {
@@ -47,26 +46,6 @@ u32 qede_osal_log2(u32 val)
        return log;
 }
 
-inline void qede_set_bit(u32 nr, unsigned long *addr)
-{
-       __sync_fetch_and_or(addr, (1UL << nr));
-}
-
-inline void qede_clr_bit(u32 nr, unsigned long *addr)
-{
-       __sync_fetch_and_and(addr, ~(1UL << nr));
-}
-
-inline bool qede_test_bit(u32 nr, unsigned long *addr)
-{
-       bool res;
-
-       rte_mb();
-       res = ((*addr) & (1UL << nr)) != 0;
-       rte_mb();
-       return res;
-}
-
 static inline u32 qede_ffb(unsigned long word)
 {
        unsigned long first_bit;
@@ -96,7 +75,7 @@ static inline u32 qede_ffz(unsigned long word)
        return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
 }
 
-inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
+inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit)
 {
        u32 i;
        u32 nwords = 0;
@@ -130,13 +109,13 @@ void *osal_dma_alloc_coherent(struct ecore_dev *p_dev,
        }
 
        OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
-       snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+       snprintf(mz_name, sizeof(mz_name), "%lx",
                                        (unsigned long)rte_get_timer_cycles());
        if (core_id == (unsigned int)LCORE_ID_ANY)
                core_id = rte_get_master_lcore();
        socket_id = rte_lcore_to_socket_id(core_id);
-       mz = rte_memzone_reserve_aligned(mz_name, size,
-                                        socket_id, 0, RTE_CACHE_LINE_SIZE);
+       mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+                       RTE_MEMZONE_IOVA_CONTIG, RTE_CACHE_LINE_SIZE);
        if (!mz) {
                DP_ERR(p_dev, "Unable to allocate DMA memory "
                       "of size %zu bytes - %s\n",
@@ -169,12 +148,13 @@ void *osal_dma_alloc_coherent_aligned(struct ecore_dev *p_dev,
        }
 
        OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
-       snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+       snprintf(mz_name, sizeof(mz_name), "%lx",
                                        (unsigned long)rte_get_timer_cycles());
        if (core_id == (unsigned int)LCORE_ID_ANY)
                core_id = rte_get_master_lcore();
        socket_id = rte_lcore_to_socket_id(core_id);
-       mz = rte_memzone_reserve_aligned(mz_name, size, socket_id, 0, align);
+       mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+                       RTE_MEMZONE_IOVA_CONTIG, align);
        if (!mz) {
                DP_ERR(p_dev, "Unable to allocate DMA memory "
                       "of size %zu bytes - %s\n",
@@ -200,6 +180,11 @@ void osal_dma_free_mem(struct ecore_dev *p_dev, dma_addr_t phys)
                        DP_VERBOSE(p_dev, ECORE_MSG_SP,
                                "Free memzone %s\n", ecore_mz_mapping[j]->name);
                        rte_memzone_free(ecore_mz_mapping[j]);
+                       while (j < ecore_mz_count - 1) {
+                               ecore_mz_mapping[j] = ecore_mz_mapping[j + 1];
+                               j++;
+                       }
+                       ecore_mz_count--;
                        return;
                }
        }
@@ -261,6 +246,28 @@ qede_get_mcp_proto_stats(struct ecore_dev *edev,
        }
 }
 
+static void qede_hw_err_handler(void *dev, enum ecore_hw_err_type err_type)
+{
+       struct ecore_dev *edev = dev;
+
+       switch (err_type) {
+       case ECORE_HW_ERR_FAN_FAIL:
+               break;
+
+       case ECORE_HW_ERR_MFW_RESP_FAIL:
+       case ECORE_HW_ERR_HW_ATTN:
+       case ECORE_HW_ERR_DMAE_FAIL:
+       case ECORE_HW_ERR_RAMROD_FAIL:
+       case ECORE_HW_ERR_FW_ASSERT:
+               OSAL_SAVE_FW_DUMP(0); /* Using port 0 as default port_id */
+               break;
+
+       default:
+               DP_NOTICE(edev, false, "Unknown HW error [%d]\n", err_type);
+               return;
+       }
+}
+
 void
 qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
 {
@@ -290,6 +297,9 @@ qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
        }
 
        DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
+
+       qede_hw_err_handler(p_hwfn->p_dev, err_type);
+
        ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
 }
 
@@ -304,3 +314,9 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
        }
        return crc;
 }
+
+void qed_set_platform_str(struct ecore_hwfn *p_hwfn,
+                         char *buf_str, u32 buf_size)
+{
+       snprintf(buf_str, buf_size, "%s.", rte_version());
+}