#include "bcm_osal.h"
#include "ecore.h"
#include "ecore_hw.h"
+#include "ecore_dev_api.h"
#include "ecore_iov_api.h"
#include "ecore_mcp_api.h"
#include "ecore_l2_api.h"
/* Array of memzone pointers */
static const struct rte_memzone *ecore_mz_mapping[RTE_MAX_MEMZONE];
/* Counter to track current memzone allocated */
-uint16_t ecore_mz_count;
+static uint16_t ecore_mz_count;
unsigned long qede_log2_align(unsigned long n)
{
return log;
}
-inline void qede_set_bit(u32 nr, unsigned long *addr)
-{
- __sync_fetch_and_or(addr, (1UL << nr));
-}
-
-inline void qede_clr_bit(u32 nr, unsigned long *addr)
-{
- __sync_fetch_and_and(addr, ~(1UL << nr));
-}
-
-inline bool qede_test_bit(u32 nr, unsigned long *addr)
-{
- bool res;
-
- rte_mb();
- res = ((*addr) & (1UL << nr)) != 0;
- rte_mb();
- return res;
-}
-
static inline u32 qede_ffb(unsigned long word)
{
unsigned long first_bit;
return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
}
-inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
+inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit)
{
u32 i;
u32 nwords = 0;
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
core_id = rte_get_master_lcore();
}
OSAL_MEM_ZERO(mz_name, sizeof(*mz_name));
- snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+ snprintf(mz_name, sizeof(mz_name), "%lx",
(unsigned long)rte_get_timer_cycles());
if (core_id == (unsigned int)LCORE_ID_ANY)
core_id = rte_get_master_lcore();
}
}
+static void qede_hw_err_handler(void *dev, enum ecore_hw_err_type err_type)
+{
+ struct ecore_dev *edev = dev;
+
+ switch (err_type) {
+ case ECORE_HW_ERR_FAN_FAIL:
+ break;
+
+ case ECORE_HW_ERR_MFW_RESP_FAIL:
+ case ECORE_HW_ERR_HW_ATTN:
+ case ECORE_HW_ERR_DMAE_FAIL:
+ case ECORE_HW_ERR_RAMROD_FAIL:
+ case ECORE_HW_ERR_FW_ASSERT:
+ OSAL_SAVE_FW_DUMP(0); /* Using port 0 as default port_id */
+ break;
+
+ default:
+ DP_NOTICE(edev, false, "Unknown HW error [%d]\n", err_type);
+ return;
+ }
+}
+
void
qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
{
}
DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
+
+ qede_hw_err_handler(p_hwfn->p_dev, err_type);
+
ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
}
}
return crc;
}
+
+void qed_set_platform_str(struct ecore_hwfn *p_hwfn,
+ char *buf_str, u32 buf_size)
+{
+ snprintf(buf_str, buf_size, "%s.", rte_version());
+}