net/af_xdp: avoid deadlock due to empty fill queue

[dpdk.git] / drivers / net / qede / base / bcm_osal.c

diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c
index 48d016e..65837b5 100644 (file)
--- a/drivers/net/qede/base/bcm_osal.c
+++ b/drivers/net/qede/base/bcm_osal.c
@@ -46,26 +46,6 @@ u32 qede_osal_log2(u32 val)
        return log;
 }
 
-inline void qede_set_bit(u32 nr, unsigned long *addr)
-{
-       __sync_fetch_and_or(addr, (1UL << nr));
-}
-
-inline void qede_clr_bit(u32 nr, unsigned long *addr)
-{
-       __sync_fetch_and_and(addr, ~(1UL << nr));
-}
-
-inline bool qede_test_bit(u32 nr, unsigned long *addr)
-{
-       bool res;
-
-       rte_mb();
-       res = ((*addr) & (1UL << nr)) != 0;
-       rte_mb();
-       return res;
-}
-
 static inline u32 qede_ffb(unsigned long word)
 {
        unsigned long first_bit;
@@ -95,7 +75,7 @@ static inline u32 qede_ffz(unsigned long word)
        return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
 }
 
-inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
+inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit)
 {
        u32 i;
        u32 nwords = 0;
@@ -266,6 +246,28 @@ qede_get_mcp_proto_stats(struct ecore_dev *edev,
        }
 }
 
+static void qede_hw_err_handler(void *dev, enum ecore_hw_err_type err_type)
+{
+       struct ecore_dev *edev = dev;
+
+       switch (err_type) {
+       case ECORE_HW_ERR_FAN_FAIL:
+               break;
+
+       case ECORE_HW_ERR_MFW_RESP_FAIL:
+       case ECORE_HW_ERR_HW_ATTN:
+       case ECORE_HW_ERR_DMAE_FAIL:
+       case ECORE_HW_ERR_RAMROD_FAIL:
+       case ECORE_HW_ERR_FW_ASSERT:
+               OSAL_SAVE_FW_DUMP(0); /* Using port 0 as default port_id */
+               break;
+
+       default:
+               DP_NOTICE(edev, false, "Unknown HW error [%d]\n", err_type);
+               return;
+       }
+}
+
 void
 qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
 {
@@ -295,6 +297,9 @@ qede_hw_err_notify(struct ecore_hwfn *p_hwfn, enum ecore_hw_err_type err_type)
        }
 
        DP_ERR(p_hwfn, "HW error occurred [%s]\n", err_str);
+
+       qede_hw_err_handler(p_hwfn->p_dev, err_type);
+
        ecore_int_attn_clr_enable(p_hwfn->p_dev, true);
 }
 
@@ -309,3 +314,9 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
        }
        return crc;
 }
+
+void qed_set_platform_str(struct ecore_hwfn *p_hwfn,
+                         char *buf_str, u32 buf_size)
+{
+       snprintf(buf_str, buf_size, "%s.", rte_version());
+}