#include <unistd.h>
#define CONFIG_ECORE_BINARY_FW
-#define CONFIG_ECORE_ZIPPED_FW
+#undef CONFIG_ECORE_ZIPPED_FW
#ifdef CONFIG_ECORE_ZIPPED_FW
#include <zlib.h>
#define SET_FIELD(value, name, flag) \
do { \
(value) &= ~(name##_MASK << name##_SHIFT); \
- (value) |= (((u64)flag) << (name##_SHIFT)); \
+ (value) |= ((((u64)flag) & (u64)name##_MASK) << (name##_SHIFT));\
} while (0)
#define GET_FIELD(value, name) \
ECORE_PORT_MODE_DE_2X25G,
ECORE_PORT_MODE_DE_1X25G,
ECORE_PORT_MODE_DE_4X25G,
+ ECORE_PORT_MODE_DE_2X10G,
};
enum ecore_dev_cap {
/* SRIOV */
struct ecore_hw_sriov_info *p_iov_info;
#define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
- bool b_hw_channel;
-
unsigned long tunn_mode;
bool b_is_vf;
bool attn_clr_en;
+ /* Indicates whether allowing the MFW to collect a crash dump */
+ bool mdump_en;
+
/* Indicates if the reg_fifo is checked after any register access */
bool chk_reg_fifo;
#define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
: MAX_NUM_PFS_K2)
-#ifndef REAL_ASIC_ONLY
-#define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
- (ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
- (ECORE_PATH_ID(p_hwfn) == 1) && \
- ((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
- (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
- (p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
-#endif
-
/**
* @brief ecore_concrete_to_sw_fid - get the sw function id from
* the concrete value.
}
#define PURE_LB_TC 8
-#define OOO_LB_TC 9
+#define PKT_LB_TC 9
int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
int ecore_device_num_engines(struct ecore_dev *p_dev);
int ecore_device_num_ports(struct ecore_dev *p_dev);
+void ecore_set_fw_mac_addr(__le16 *fw_msb, __le16 *fw_mid, __le16 *fw_lsb,
+ u8 *mac);
#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])