-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
* All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
*/
#ifndef __ECORE_H
#include <zlib.h>
#endif
+#include "ecore_status.h"
#include "ecore_hsi_common.h"
#include "ecore_hsi_debug_tools.h"
#include "ecore_hsi_init_func.h"
#include "mcp_public.h"
#define ECORE_MAJOR_VERSION 8
-#define ECORE_MINOR_VERSION 18
-#define ECORE_REVISION_VERSION 7
-#define ECORE_ENGINEERING_VERSION 1
+#define ECORE_MINOR_VERSION 37
+#define ECORE_REVISION_VERSION 20
+#define ECORE_ENGINEERING_VERSION 0
#define ECORE_VERSION \
((ECORE_MAJOR_VERSION << 24) | (ECORE_MINOR_VERSION << 16) | \
((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
(FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
+#define IS_ECORE_PACING(p_hwfn) \
+ (!!(p_hwfn->b_en_pacing))
+
#define MAX_HWFNS_PER_DEVICE 2
#define NAME_SIZE 128 /* @DPDK */
#define ECORE_WFQ_UNIT 100
#define FCOE_BDQ_ID(_port_id) (_port_id + 2)
/* Constants */
#define ECORE_WID_SIZE (1024)
+#define ECORE_MIN_WIDS (4)
/* Configurable */
#define ECORE_PF_DEMS_SIZE (4)
struct ecore_igu_info;
struct ecore_mcp_info;
struct ecore_dcbx_info;
+struct ecore_llh_info;
struct ecore_rt_data {
u32 *init_val;
struct ecore_hw_info {
/* PCI personality */
enum ecore_pci_personality personality;
-#define ECORE_IS_RDMA_PERSONALITY(dev) \
- ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
+#define ECORE_IS_RDMA_PERSONALITY(dev) \
+ ((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
(dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
(dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
-#define ECORE_IS_ROCE_PERSONALITY(dev) \
+#define ECORE_IS_ROCE_PERSONALITY(dev) \
((dev)->hw_info.personality == ECORE_PCI_ETH_ROCE || \
(dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
-#define ECORE_IS_IWARP_PERSONALITY(dev) \
+#define ECORE_IS_IWARP_PERSONALITY(dev) \
((dev)->hw_info.personality == ECORE_PCI_ETH_IWARP || \
(dev)->hw_info.personality == ECORE_PCI_ETH_RDMA)
-#define ECORE_IS_L2_PERSONALITY(dev) \
+#define ECORE_IS_L2_PERSONALITY(dev) \
((dev)->hw_info.personality == ECORE_PCI_ETH || \
ECORE_IS_RDMA_PERSONALITY(dev))
+#define ECORE_IS_FCOE_PERSONALITY(dev) \
+ ((dev)->hw_info.personality == ECORE_PCI_FCOE)
+#define ECORE_IS_ISCSI_PERSONALITY(dev) \
+ ((dev)->hw_info.personality == ECORE_PCI_ISCSI)
/* Resource Allocation scheme results */
u32 resc_start[ECORE_MAX_RESC];
#define DMAE_MAX_RW_SIZE 0x2000
struct ecore_dmae_info {
- /* Mutex for synchronizing access to functions */
- osal_mutex_t mutex;
+ /* Spinlock for synchronizing access to functions */
+ osal_spinlock_t lock;
+
+ bool b_mem_ready;
u8 channel;
u32 init_ops_size;
};
+enum ecore_mf_mode_bit {
+ /* Supports PF-classification based on tag */
+ ECORE_MF_OVLAN_CLSS,
+
+ /* Supports PF-classification based on MAC */
+ ECORE_MF_LLH_MAC_CLSS,
+
+ /* Supports PF-classification based on protocol type */
+ ECORE_MF_LLH_PROTO_CLSS,
+
+ /* Requires a default PF to be set */
+ ECORE_MF_NEED_DEF_PF,
+
+ /* Allow LL2 to multicast/broadcast */
+ ECORE_MF_LL2_NON_UNICAST,
+
+ /* Allow Cross-PF [& child VFs] Tx-switching */
+ ECORE_MF_INTER_PF_SWITCH,
+
+ /* TODO - if we ever re-utilize any of this logic, we can rename */
+ ECORE_MF_UFP_SPECIFIC,
+
+ ECORE_MF_DISABLE_ARFS,
+
+ /* Use vlan for steering */
+ ECORE_MF_8021Q_TAGGING,
+
+ /* Use stag for steering */
+ ECORE_MF_8021AD_TAGGING,
+
+ /* Allow FIP discovery fallback */
+ ECORE_MF_FIP_SPECIAL,
+};
+
+enum ecore_ufp_mode {
+ ECORE_UFP_MODE_ETS,
+ ECORE_UFP_MODE_VNIC_BW,
+};
+
+enum ecore_ufp_pri_type {
+ ECORE_UFP_PRI_OS,
+ ECORE_UFP_PRI_VNIC
+};
+
+struct ecore_ufp_info {
+ enum ecore_ufp_pri_type pri_type;
+ enum ecore_ufp_mode mode;
+ u8 tc;
+};
+
+enum BAR_ID {
+ BAR_ID_0, /* used for GRC */
+ BAR_ID_1 /* Used for doorbells */
+};
+
struct ecore_hwfn {
struct ecore_dev *p_dev;
u8 my_id; /* ID inside the PF */
#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
u8 rel_pf_id; /* Relative to engine*/
u8 abs_pf_id;
- #define ECORE_PATH_ID(_p_hwfn) \
- (ECORE_IS_K2((_p_hwfn)->p_dev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
+#define ECORE_PATH_ID(_p_hwfn) \
+ (ECORE_IS_BB((_p_hwfn)->p_dev) ? ((_p_hwfn)->abs_pf_id & 1) : 0)
u8 port_id;
bool b_active;
struct ecore_pf_iov *pf_iov_info;
struct ecore_mcp_info *mcp_info;
struct ecore_dcbx_info *p_dcbx_info;
+ struct ecore_ufp_info ufp_info;
struct ecore_dmae_info dmae_info;
#endif
struct dbg_tools_data dbg_info;
+ void *dbg_user_info;
struct z_stream_s *stream;
/* Mechanism for recovering from doorbell drop */
struct ecore_db_recovery_info db_recovery_info;
+ /* Enable/disable pacing, if request to enable then
+ * IOV and mcos configuration will be skipped.
+ * this actually reflects the value requested in
+ * struct ecore_hw_prepare_params by ecore client.
+ */
+ bool b_en_pacing;
+
/* @DPDK */
struct ecore_ptt *p_arfs_ptt;
};
-#ifndef __EXTRACT__LINUX__
enum ecore_mf_mode {
ECORE_MF_DEFAULT,
ECORE_MF_OVLAN,
ECORE_MF_NPAR,
+ ECORE_MF_UFP,
};
-#endif
/* @DPDK */
struct ecore_dbg_feature {
#endif
#define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
#define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
+#define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev))
u16 vendor_id;
u16 device_id;
#define CHIP_BOND_ID_SHIFT 0
u8 num_engines;
- u8 num_ports_in_engines;
+ u8 num_ports;
+ u8 num_ports_in_engine;
u8 num_funcs_in_port;
u8 path_id;
+
+ unsigned long mf_bits;
enum ecore_mf_mode mf_mode;
#define IS_MF_DEFAULT(_p_hwfn) \
(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
u8 cache_shift;
/* Init */
- const struct iro *iro_arr;
- #define IRO (p_hwfn->p_dev->iro_arr)
+ const u32 *iro_arr;
+#define IRO ((const struct iro *)p_hwfn->p_dev->iro_arr)
/* HW functions */
u8 num_hwfns;
struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
+#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
+#define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
+
+ /* Engine affinity */
+ u8 l2_affin_hint;
+ u8 fir_affin;
+ u8 iwarp_affin;
+ /* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
+#define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
+ /* Macro for getting the engine-affinitized hwfn for iWARP */
+#define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
+ /* Generic macro for getting the engine-affinitized hwfn */
+#define ECORE_AFFIN_HWFN(dev) \
+ (ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
+ ECORE_IWARP_AFFIN_HWFN(dev) : \
+ ECORE_FIR_AFFIN_HWFN(dev))
+ /* Macro for getting the index (0/1) of the engine-affinitized hwfn */
+#define ECORE_AFFIN_HWFN_IDX(dev) \
+ (IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
/* SRIOV */
struct ecore_hw_sriov_info *p_iov_info;
#ifndef ASIC_ONLY
bool b_is_emul_full;
#endif
+ /* LLH info */
+ u8 ppfid_bitmap;
+ struct ecore_llh_info *p_llh_info;
+
+ /* Indicates whether this PF serves a storage target */
+ bool b_is_target;
#ifdef CONFIG_ECORE_BINARY_FW /* @DPDK */
void *firmware;
#define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
: MAX_NUM_PFS_K2)
+#define CRC8_TABLE_SIZE 256
+
/**
* @brief ecore_concrete_to_sw_fid - get the sw function id from
* the concrete value.
return sw_fid;
}
-#define PURE_LB_TC 8
#define PKT_LB_TC 9
+#define MAX_NUM_VOQS_E4 20
int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
#define PQ_FLAGS_ACK (1 << 4)
#define PQ_FLAGS_OFLD (1 << 5)
#define PQ_FLAGS_VFS (1 << 6)
+#define PQ_FLAGS_LLT (1 << 7)
/* physical queue index for cm context intialization */
u16 ecore_get_cm_pq_idx(struct ecore_hwfn *p_hwfn, u32 pq_flags);
u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc);
u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf);
-u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u8 qpid);
+u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
+
+/* qm vport for rate limit configuration */
+u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl);
const char *ecore_hw_get_resc_name(enum ecore_resources res_id);
void ecore_db_recovery_execute(struct ecore_hwfn *p_hwfn,
enum ecore_db_rec_exec);
+bool ecore_edpm_enabled(struct ecore_hwfn *p_hwfn);
+
/* amount of resources used in qm init */
u8 ecore_init_qm_get_num_tcs(struct ecore_hwfn *p_hwfn);
u16 ecore_init_qm_get_num_vfs(struct ecore_hwfn *p_hwfn);
u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
-#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
+#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
+ ecore_device_num_ports((_p_hwfn)->p_dev))
+
+/* The PFID<->PPFID calculation is based on the relative index of a PF on its
+ * port. In BB there is a bug in the LLH in which the PPFID is actually engine
+ * based, and thus it equals the PFID.
+ */
+#define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
+ (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
+ (abs_ppfid) : \
+ (abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
+ MFW_PORT(_p_hwfn))
+#define ECORE_PPFID_BY_PFID(_p_hwfn) \
+ (ECORE_IS_BB((_p_hwfn)->p_dev) ? \
+ (_p_hwfn)->rel_pf_id : \
+ (_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
+
+enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
+ struct ecore_ptt *p_ptt, u32 addr,
+ u32 val);
+
+/* Utility functions for dumping the content of the NIG LLH filters */
+enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
+enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
#endif /* __ECORE_H */
git.droids-corp.org / dpdk.git / blobdiff