qede: add interrupt handling support

[dpdk.git] / drivers / net / qede / base / ecore_dev.c

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 5c0d618..0ded161 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -29,6 +29,7 @@
 #include "ecore_iro.h"
 #include "nvm_cfg.h"
 #include "ecore_dev_api.h"
+#include "ecore_attn_values.h"
 
 /* Configurable */
 #define ECORE_MIN_DPIS         (4)     /* The minimal number of DPIs required
@@ -676,6 +677,37 @@ static void ecore_hw_init_chip(struct ecore_hwfn *p_hwfn,
        if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) && ECORE_IS_AH(p_hwfn->p_dev))
                ecore_wr(p_hwfn, p_ptt, MISCS_REG_RESET_PL_HV_2, 0x3ffffff);
 
+       /* initialize interrupt masks */
+       for (i = 0;
+            i <
+            attn_blocks[BLOCK_MISCS].chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].
+            num_of_int_regs; i++)
+               ecore_wr(p_hwfn, p_ptt,
+                        attn_blocks[BLOCK_MISCS].
+                        chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[i]->
+                        mask_addr, 0);
+
+       if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
+               ecore_wr(p_hwfn, p_ptt,
+                        attn_blocks[BLOCK_CNIG].
+                        chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
+                        mask_addr, 0);
+       ecore_wr(p_hwfn, p_ptt,
+                attn_blocks[BLOCK_PGLCS].
+                chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
+                mask_addr, 0);
+       ecore_wr(p_hwfn, p_ptt,
+                attn_blocks[BLOCK_CPMU].
+                chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
+                mask_addr, 0);
+       /* Currently A0 and B0 interrupt bits are the same in pglue_b;
+        * If this changes, need to set this according to chip type. <14/09/23>
+        */
+       ecore_wr(p_hwfn, p_ptt,
+                attn_blocks[BLOCK_PGLUE_B].
+                chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].int_regs[0]->
+                mask_addr, 0x80000);
+
        /* initialize port mode to 4x10G_E (10G with 4x10 SERDES) */
        /* CNIG_REG_NW_PORT_MODE is same for A0 and B0 */
        if (!CHIP_REV_IS_EMUL(p_hwfn->p_dev) || !ECORE_IS_AH(p_hwfn->p_dev))
@@ -1182,6 +1214,25 @@ ecore_hw_init_pf(struct ecore_hwfn *p_hwfn,
         *                           &ctrl);
         */
 
+#ifndef ASIC_ONLY
+       /*@@TMP - On B0 build 1, need to mask the datapath_registers parity */
+       if (CHIP_REV_IS_EMUL_B0(p_hwfn->p_dev) &&
+           (p_hwfn->p_dev->chip_metal == 1)) {
+               u32 reg_addr, tmp;
+
+               reg_addr =
+                   attn_blocks[BLOCK_PGLUE_B].
+                   chip_regs[ECORE_GET_TYPE(p_hwfn->p_dev)].prty_regs[0]->
+                   mask_addr;
+               DP_NOTICE(p_hwfn, false,
+                         "Masking datapath registers parity on"
+                         " B0 emulation [build 1]\n");
+               tmp = ecore_rd(p_hwfn, p_ptt, reg_addr);
+               tmp |= (1 << 0);        /* Was PRTY_MASK_DATAPATH_REGISTERS */
+               ecore_wr(p_hwfn, p_ptt, reg_addr, tmp);
+       }
+#endif
+
        rc = ecore_hw_init_pf_doorbell_bar(p_hwfn, p_ptt);
        if (rc)
                return rc;