net/qede/base: get pre-negotiated OEM values

[dpdk.git] / drivers / net / qede / base / ecore_dev.c

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index f09f771..30e12e9 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -569,12 +569,11 @@ u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn)
 {
        u16 num_pf_rls, num_vfs = ecore_init_qm_get_num_vfs(p_hwfn);
 
-       /* @DPDK */
        /* num RLs can't exceed resource amount of rls or vports or the
         * dcqcn qps
         */
        num_pf_rls = (u16)OSAL_MIN_T(u32, RESC_NUM(p_hwfn, ECORE_RL),
-                                    (u16)RESC_NUM(p_hwfn, ECORE_VPORT));
+                                    RESC_NUM(p_hwfn, ECORE_VPORT));
 
        /* make sure after we reserve the default and VF rls we'll have
         * something left
@@ -835,7 +834,7 @@ u16 ecore_get_cm_pq_idx_mcos(struct ecore_hwfn *p_hwfn, u8 tc)
        if (tc > max_tc)
                DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc);
 
-       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc;
+       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc);
 }
 
 u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
@@ -845,17 +844,17 @@ u16 ecore_get_cm_pq_idx_vf(struct ecore_hwfn *p_hwfn, u16 vf)
        if (vf > max_vf)
                DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf);
 
-       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf;
+       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf);
 }
 
 u16 ecore_get_cm_pq_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
 {
        u16 max_rl = ecore_init_qm_get_num_pf_rls(p_hwfn);
 
-       if (rl > max_rl)
-               DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl);
-
-       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl;
+       /* for rate limiters, it is okay to use the modulo behavior - no
+        * DP_ERR
+        */
+       return ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + (rl % max_rl);
 }
 
 u16 ecore_get_qm_vport_idx_rl(struct ecore_hwfn *p_hwfn, u16 rl)
@@ -2646,6 +2645,20 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
                                  "Failed to send GET_OEM_UPDATES attention request\n");
        }
 
+       if (IS_PF(p_dev)) {
+               /* Get pre-negotiated values for stag, bandwidth etc. */
+               p_hwfn = ECORE_LEADING_HWFN(p_dev);
+               DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
+                          "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n");
+               rc = ecore_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt,
+                                  DRV_MSG_CODE_GET_OEM_UPDATES,
+                                  1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET,
+                                  &resp, &param);
+               if (rc != ECORE_SUCCESS)
+                       DP_NOTICE(p_hwfn, false,
+                                 "Failed to send GET_OEM_UPDATES attention request\n");
+       }
+
        if (IS_PF(p_dev)) {
                p_hwfn = ECORE_LEADING_HWFN(p_dev);
                drv_mb_param = STORM_FW_VERSION;
@@ -2804,6 +2817,12 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
                        rc2 = ECORE_UNKNOWN_ERROR;
                }
 
+               OSAL_DPC_SYNC(p_hwfn);
+
+               /* After this point we don't expect the FW to send us async
+                * events
+                */
+
                /* perform debug action after PF stop was sent */
                OSAL_AFTER_PF_STOP((void *)p_dev, p_hwfn->my_id);
 
@@ -3698,7 +3717,8 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
        case NVM_CFG1_GLOB_MF_MODE_BD:
                p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_OVLAN_CLSS |
                                         1 << ECORE_MF_LLH_PROTO_CLSS |
-                                        1 << ECORE_MF_8021AD_TAGGING;
+                                        1 << ECORE_MF_8021AD_TAGGING |
+                                        1 << ECORE_MF_FIP_SPECIAL;
                break;
        case NVM_CFG1_GLOB_MF_MODE_NPAR1_0:
                p_hwfn->p_dev->mf_bits = 1 << ECORE_MF_LLH_MAC_CLSS |
@@ -5798,3 +5818,8 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb,
        ((u8 *)fw_lsb)[0] = mac[5];
        ((u8 *)fw_lsb)[1] = mac[4];
 }
+
+bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
+{
+       return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
+}