net/qede/base: improve Tx-switching performance

[dpdk.git] / drivers / net / qede / base / ecore_dev.c

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index b530173..8b7d1da 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -542,11 +542,14 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
        /* Allocate Memory for the Queue->CID mapping */
        for_each_hwfn(p_dev, i) {
                struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
+               u32 num_tx_conns = RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
+               int tx_size, rx_size;
 
                /* @@@TMP - resc management, change to actual required size */
-               int tx_size = sizeof(struct ecore_hw_cid_data) *
-                   RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
-               int rx_size = sizeof(struct ecore_hw_cid_data) *
+               if (p_hwfn->pf_params.eth_pf_params.num_cons > num_tx_conns)
+                       num_tx_conns = p_hwfn->pf_params.eth_pf_params.num_cons;
+               tx_size = sizeof(struct ecore_hw_cid_data) * num_tx_conns;
+               rx_size = sizeof(struct ecore_hw_cid_data) *
                    RESC_NUM(p_hwfn, ECORE_L2_QUEUE);
 
                p_hwfn->p_tx_cids = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
@@ -667,6 +670,7 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
                        DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
                                       "The maximum of a u16 chain is 0x%x\n",
                               n_eqes, 0xFFFF);
+                       rc = ECORE_INVAL;
                        goto alloc_err;
                }
 
@@ -2952,13 +2956,14 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                        void OSAL_IOMEM *p_doorbells,
                        struct ecore_hw_prepare_params *p_params)
 {
+       struct ecore_dev *p_dev = p_hwfn->p_dev;
        enum _ecore_status_t rc = ECORE_SUCCESS;
 
        /* Split PCI bars evenly between hwfns */
        p_hwfn->regview = p_regview;
        p_hwfn->doorbells = p_doorbells;
 
-       if (IS_VF(p_hwfn->p_dev))
+       if (IS_VF(p_dev))
                return ecore_vf_hw_prepare(p_hwfn);
 
        /* Validate that chip access is feasible */
@@ -2982,7 +2987,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
 
        /* First hwfn learns basic information, e.g., number of hwfns */
        if (!p_hwfn->my_id) {
-               rc = ecore_get_dev_info(p_hwfn->p_dev);
+               rc = ecore_get_dev_info(p_dev);
                if (rc != ECORE_SUCCESS)
                        goto err1;
        }
@@ -3004,6 +3009,16 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                goto err2;
        }
 
+       /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
+        * called, since among others it sets the ports number in an engine.
+        */
+       if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
+           !p_dev->recov_in_prog) {
+               rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
+               if (rc != ECORE_SUCCESS)
+                       DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
+       }
+
        /* Allocate the init RT array and initialize the init-ops engine */
        rc = ecore_init_alloc(p_hwfn);
        if (rc) {
@@ -3011,7 +3026,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                goto err2;
        }
 #ifndef ASIC_ONLY
-       if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
+       if (CHIP_REV_IS_FPGA(p_dev)) {
                DP_NOTICE(p_hwfn, false,
                          "FPGA: workaround; Prevent DMAE parities\n");
                ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
@@ -3026,7 +3041,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
        return rc;
  err2:
        if (IS_LEAD_HWFN(p_hwfn))
-               ecore_iov_free_hw_info(p_hwfn->p_dev);
+               ecore_iov_free_hw_info(p_dev);
        ecore_mcp_free(p_hwfn);
  err1:
        ecore_hw_hwfn_free(p_hwfn);
@@ -4285,3 +4300,16 @@ int ecore_device_num_ports(struct ecore_dev *p_dev)
 
        return p_dev->num_ports_in_engines * ecore_device_num_engines(p_dev);
 }
+
+void ecore_set_fw_mac_addr(__le16 *fw_msb,
+                         __le16 *fw_mid,
+                         __le16 *fw_lsb,
+                         u8 *mac)
+{
+       ((u8 *)fw_msb)[0] = mac[1];
+       ((u8 *)fw_msb)[1] = mac[0];
+       ((u8 *)fw_mid)[0] = mac[3];
+       ((u8 *)fw_mid)[1] = mac[2];
+       ((u8 *)fw_lsb)[0] = mac[5];
+       ((u8 *)fw_lsb)[1] = mac[4];
+}