net/qede/base: improve set field macro

[dpdk.git] / drivers / net / qede / base / ecore_dev.c

diff --git a/drivers/net/qede/base/ecore_dev.c b/drivers/net/qede/base/ecore_dev.c
index 319edeb..d7a95fe 100644 (file)
--- a/drivers/net/qede/base/ecore_dev.c
+++ b/drivers/net/qede/base/ecore_dev.c
@@ -667,6 +667,7 @@ enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
                        DP_ERR(p_hwfn, "Cannot allocate 0x%x EQ elements."
                                       "The maximum of a u16 chain is 0x%x\n",
                               n_eqes, 0xFFFF);
+                       rc = ECORE_INVAL;
                        goto alloc_err;
                }
 
@@ -1619,24 +1620,20 @@ static void ecore_reset_mb_shadow(struct ecore_hwfn *p_hwfn,
 }
 
 enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
-                                  struct ecore_tunn_start_params *p_tunn,
-                                  bool b_hw_start,
-                                  enum ecore_int_mode int_mode,
-                                  bool allow_npar_tx_switch,
-                                  const u8 *bin_fw_data)
+                                  struct ecore_hw_init_params *p_params)
 {
        enum _ecore_status_t rc, mfw_rc;
        u32 load_code, param;
        int i, j;
 
-       if ((int_mode == ECORE_INT_MODE_MSI) && (p_dev->num_hwfns > 1)) {
+       if (p_params->int_mode == ECORE_INT_MODE_MSI && p_dev->num_hwfns > 1) {
                DP_NOTICE(p_dev, false,
                          "MSI mode is not supported for CMT devices\n");
                return ECORE_INVAL;
        }
 
        if (IS_PF(p_dev)) {
-               rc = ecore_init_fw_data(p_dev, bin_fw_data);
+               rc = ecore_init_fw_data(p_dev, p_params->bin_fw_data);
                if (rc != ECORE_SUCCESS)
                        return rc;
        }
@@ -1733,9 +1730,11 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
                        /* Fall into */
                case FW_MSG_CODE_DRV_LOAD_FUNCTION:
                        rc = ecore_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt,
-                                             p_tunn, p_hwfn->hw_info.hw_mode,
-                                             b_hw_start, int_mode,
-                                             allow_npar_tx_switch);
+                                             p_params->p_tunn,
+                                             p_hwfn->hw_info.hw_mode,
+                                             p_params->b_hw_start,
+                                             p_params->int_mode,
+                                             p_params->allow_npar_tx_switch);
                        break;
                default:
                        rc = ECORE_NOTIMPL;
@@ -1759,6 +1758,10 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
                        return mfw_rc;
                }
 
+               ecore_mcp_mdump_get_info(p_hwfn, p_hwfn->p_main_ptt);
+               ecore_mcp_mdump_set_values(p_hwfn, p_hwfn->p_main_ptt,
+                                          p_params->epoch);
+
                /* send DCBX attention request command */
                DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
                           "sending phony dcbx set command to trigger DCBx attention handling\n");
@@ -2950,13 +2953,14 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                        void OSAL_IOMEM *p_doorbells,
                        struct ecore_hw_prepare_params *p_params)
 {
+       struct ecore_dev *p_dev = p_hwfn->p_dev;
        enum _ecore_status_t rc = ECORE_SUCCESS;
 
        /* Split PCI bars evenly between hwfns */
        p_hwfn->regview = p_regview;
        p_hwfn->doorbells = p_doorbells;
 
-       if (IS_VF(p_hwfn->p_dev))
+       if (IS_VF(p_dev))
                return ecore_vf_hw_prepare(p_hwfn);
 
        /* Validate that chip access is feasible */
@@ -2980,7 +2984,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
 
        /* First hwfn learns basic information, e.g., number of hwfns */
        if (!p_hwfn->my_id) {
-               rc = ecore_get_dev_info(p_hwfn->p_dev);
+               rc = ecore_get_dev_info(p_dev);
                if (rc != ECORE_SUCCESS)
                        goto err1;
        }
@@ -3002,6 +3006,16 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                goto err2;
        }
 
+       /* Sending a mailbox to the MFW should be after ecore_get_hw_info() is
+        * called, since among others it sets the ports number in an engine.
+        */
+       if (p_params->initiate_pf_flr && p_hwfn == ECORE_LEADING_HWFN(p_dev) &&
+           !p_dev->recov_in_prog) {
+               rc = ecore_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt);
+               if (rc != ECORE_SUCCESS)
+                       DP_NOTICE(p_hwfn, false, "Failed to initiate PF FLR\n");
+       }
+
        /* Allocate the init RT array and initialize the init-ops engine */
        rc = ecore_init_alloc(p_hwfn);
        if (rc) {
@@ -3009,7 +3023,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
                goto err2;
        }
 #ifndef ASIC_ONLY
-       if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
+       if (CHIP_REV_IS_FPGA(p_dev)) {
                DP_NOTICE(p_hwfn, false,
                          "FPGA: workaround; Prevent DMAE parities\n");
                ecore_wr(p_hwfn, p_hwfn->p_main_ptt, PCIE_REG_PRTY_MASK, 7);
@@ -3024,7 +3038,7 @@ ecore_hw_prepare_single(struct ecore_hwfn *p_hwfn, void OSAL_IOMEM *p_regview,
        return rc;
  err2:
        if (IS_LEAD_HWFN(p_hwfn))
-               ecore_iov_free_hw_info(p_hwfn->p_dev);
+               ecore_iov_free_hw_info(p_dev);
        ecore_mcp_free(p_hwfn);
  err1:
        ecore_hw_hwfn_free(p_hwfn);