ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
}
- if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
+ if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
rc = ecore_llh_add_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
filter_details.enable = 1;
filter_details.value = ((u64)high << 32) | low;
filter_details.hdr_sel =
- OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
+ OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1 : /* inner/encapsulated header */
0; /* outer/tunnel header */
filter_details.protocol_type = filter_prot_type;
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
- !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
+ !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
{
u8 ppfid;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
- !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
+ !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
return;
for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
ecore_dmae_info_free(p_hwfn);
ecore_dcbx_info_free(p_hwfn);
ecore_dbg_user_data_free(p_hwfn);
+ ecore_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem);
/* @@@TBD Flush work-queue ? */
/* destroy doorbell recovery mechanism */
enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
+ enum dbg_status debug_status = DBG_STATUS_OK;
int i;
if (IS_VF(p_dev)) {
goto alloc_err;
}
- rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
- if (rc) {
+ debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
+ &p_hwfn->dbg_user_info);
+ if (debug_status) {
DP_NOTICE(p_hwfn, false,
"Failed to allocate dbg user info structure\n");
+ rc = (enum _ecore_status_t)debug_status;
goto alloc_err;
}
- rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
- if (rc) {
+ debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
+ &p_hwfn->dbg_user_info);
+ if (debug_status) {
DP_NOTICE(p_hwfn, false,
"Failed to allocate dbg user info structure\n");
+ rc = (enum _ecore_status_t)debug_status;
goto alloc_err;
}
} /* hwfn loop */
return ECORE_INVAL;
}
- if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
+ if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
hw_mode |= 1 << MODE_MF_SD;
else
hw_mode |= 1 << MODE_MF_SI;
return ECORE_IO;
}
- OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);
wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
* The ppfid should be set in the vector, except in BB which has
* a bug in the LLH where the ppfid is actually engine based.
*/
- if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
+ if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
u8 pf_id = p_hwfn->rel_pf_id;
if (!ECORE_IS_BB(p_dev))
if (rc)
return rc;
+ ecore_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem);
+
/* Pure runtime initializations - directly to the HW */
ecore_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true);
if (IS_LEAD_HWFN(p_hwfn)) {
rc = ecore_llh_hw_init_pf(p_hwfn, p_ptt,
p_params->avoid_eng_affin);
- if (rc)
+ if (rc != ECORE_SUCCESS)
return rc;
}
if (rc) {
DP_NOTICE(p_hwfn, true,
"Function start ramrod failed\n");
- } else {
return rc;
}
prs_reg = ecore_rd(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1);
u32 load_code, resp, param, drv_mb_param;
bool b_default_mtu = true;
struct ecore_hwfn *p_hwfn;
+ const u32 *fw_overlays;
+ u32 fw_overlays_len;
enum _ecore_status_t rc = ECORE_SUCCESS;
u16 ether_type;
int i;
if (rc != ECORE_SUCCESS)
return rc;
- if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
+ if (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits) ||
- OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
+ OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,
&p_dev->mf_bits))) {
- if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
+ if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits))
ether_type = ETHER_TYPE_VLAN;
else
*/
ecore_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt);
+ fw_overlays = p_dev->fw_data->fw_overlays;
+ fw_overlays_len = p_dev->fw_data->fw_overlays_len;
+ p_hwfn->fw_overlay_mem =
+ ecore_fw_overlay_mem_alloc(p_hwfn, fw_overlays,
+ fw_overlays_len);
+ if (!p_hwfn->fw_overlay_mem) {
+ DP_NOTICE(p_hwfn, false,
+ "Failed to allocate fw overlay memory\n");
+ goto load_err;
+ }
+
switch (load_code) {
case FW_MSG_CODE_DRV_LOAD_ENGINE:
rc = ecore_hw_init_common(p_hwfn, p_hwfn->p_main_ptt,
OSAL_MSLEEP(1);
if (IS_LEAD_HWFN(p_hwfn) &&
- OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
+ OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn))
ecore_llh_remove_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
break;
}
- DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
+ DP_INFO(p_hwfn, "Multi function mode is 0x%x\n",
p_hwfn->p_dev->mf_bits);
if (ECORE_IS_CMT(p_hwfn->p_dev))
/* MISCS_REG_ECO_RESERVED[15:12]: num of ports in an engine */
eco_reserved = ecore_rd(p_hwfn, p_ptt, MISCS_REG_ECO_RESERVED);
-
switch ((eco_reserved & 0xf000) >> 12) {
case 1:
p_dev->num_ports_in_engine = 1;
DP_NOTICE(p_hwfn, false,
"Emulation: Unknown port mode [ECO_RESERVED 0x%08x]\n",
eco_reserved);
- p_dev->num_ports_in_engine = 2; /* Default to something */
+ p_dev->num_ports_in_engine = 1; /* Default to something */
break;
}
static void ecore_hw_info_port_num(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
+ u32 addr, global_offsize, global_addr, port_mode;
struct ecore_dev *p_dev = p_hwfn->p_dev;
- u32 addr, global_offsize, global_addr;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_TEDIBEAR(p_dev)) {
return;
}
- addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
- PUBLIC_GLOBAL);
- global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
- global_addr = SECTION_ADDR(global_offsize, 0);
- addr = global_addr + OFFSETOF(struct public_global, max_ports);
- p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
+ /* Determine the number of ports per engine */
+ port_mode = ecore_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE);
+ switch (port_mode) {
+ case 0x0:
+ p_dev->num_ports_in_engine = 1;
+ break;
+ case 0x1:
+ p_dev->num_ports_in_engine = 2;
+ break;
+ case 0x2:
+ p_dev->num_ports_in_engine = 4;
+ break;
+ default:
+ DP_NOTICE(p_hwfn, false, "Unknown port mode 0x%08x\n",
+ port_mode);
+ p_dev->num_ports_in_engine = 1; /* Default to something */
+ break;
+ }
- p_dev->num_ports_in_engine = p_dev->num_ports >>
- (ecore_device_num_engines(p_dev) - 1);
+ /* Get the total number of ports of the device */
+ addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
+ PUBLIC_GLOBAL);
+ global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
+ global_addr = SECTION_ADDR(global_offsize, 0);
+ addr = global_addr + OFFSETOF(struct public_global, max_ports);
+ p_dev->num_ports = (u8)ecore_rd(p_hwfn, p_ptt, addr);
}
static void ecore_mcp_get_eee_caps(struct ecore_hwfn *p_hwfn,
u32 tmp;
/* Read Vendor Id / Device Id */
- OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID,
&p_dev->vendor_id);
- OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID,
&p_dev->device_id);
/* Determine type */
p_hwfn->db_phys_addr = db_phys_addr;
if (IS_VF(p_dev))
- return ecore_vf_hw_prepare(p_hwfn);
+ return ecore_vf_hw_prepare(p_hwfn, p_params);
/* Validate that chip access is feasible */
if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) {
ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
- if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
+ if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
1 << p_hwfn->abs_pf_id / 2);
((u8 *)fw_lsb)[1] = mac[4];
}
+void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
+ char *buf_str, u32 buf_size)
+{
+ u32 len;
+
+ OSAL_SNPRINTF(buf_str, buf_size, "Ecore %d.%d.%d.%d. ",
+ ECORE_MAJOR_VERSION, ECORE_MINOR_VERSION,
+ ECORE_REVISION_VERSION, ECORE_ENGINEERING_VERSION);
+
+ len = OSAL_STRLEN(buf_str);
+ OSAL_SET_PLATFORM_STR(p_hwfn, &buf_str[len], buf_size - len);
+}
+
bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
{
- return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
+ return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
}