ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
}
- if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
+ if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
rc = ecore_llh_add_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
filter_details.enable = 1;
filter_details.value = ((u64)high << 32) | low;
filter_details.hdr_sel =
- OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
+ OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1 : /* inner/encapsulated header */
0; /* outer/tunnel header */
filter_details.protocol_type = filter_prot_type;
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
if (p_ptt == OSAL_NULL)
return;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
- !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
+ !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
{
u8 ppfid;
- if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
- !OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
+ if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
+ !OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
return;
for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
enum _ecore_status_t ecore_resc_alloc(struct ecore_dev *p_dev)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
+ enum dbg_status debug_status = DBG_STATUS_OK;
int i;
if (IS_VF(p_dev)) {
goto alloc_err;
}
- rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
- if (rc) {
+ debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
+ &p_hwfn->dbg_user_info);
+ if (debug_status) {
DP_NOTICE(p_hwfn, false,
"Failed to allocate dbg user info structure\n");
+ rc = (enum _ecore_status_t)debug_status;
goto alloc_err;
}
- rc = OSAL_DBG_ALLOC_USER_DATA(p_hwfn, &p_hwfn->dbg_user_info);
- if (rc) {
+ debug_status = OSAL_DBG_ALLOC_USER_DATA(p_hwfn,
+ &p_hwfn->dbg_user_info);
+ if (debug_status) {
DP_NOTICE(p_hwfn, false,
"Failed to allocate dbg user info structure\n");
+ rc = (enum _ecore_status_t)debug_status;
goto alloc_err;
}
} /* hwfn loop */
return ECORE_INVAL;
}
- if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
+ if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
hw_mode |= 1 << MODE_MF_SD;
else
hw_mode |= 1 << MODE_MF_SI;
return ECORE_IO;
}
- OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + PCI_EXP_DEVCTL, &ctrl);
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, pos + RTE_PCI_EXP_DEVCTL, &ctrl);
wr_mbs = (ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
ecore_wr(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0, wr_mbs);
* The ppfid should be set in the vector, except in BB which has
* a bug in the LLH where the ppfid is actually engine based.
*/
- if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
+ if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
u8 pf_id = p_hwfn->rel_pf_id;
if (!ECORE_IS_BB(p_dev))
if (rc != ECORE_SUCCESS)
return rc;
- if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
+ if (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits) ||
- OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
+ OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,
&p_dev->mf_bits))) {
- if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
+ if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits))
ether_type = ETHER_TYPE_VLAN;
else
OSAL_MSLEEP(1);
if (IS_LEAD_HWFN(p_hwfn) &&
- OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
+ OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn))
ecore_llh_remove_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
break;
}
- DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
+ DP_INFO(p_hwfn, "Multi function mode is 0x%x\n",
p_hwfn->p_dev->mf_bits);
if (ECORE_IS_CMT(p_hwfn->p_dev))
u32 tmp;
/* Read Vendor Id / Device Id */
- OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_VENDOR_ID_OFFSET,
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_VENDOR_ID,
&p_dev->vendor_id);
- OSAL_PCI_READ_CONFIG_WORD(p_dev, PCICFG_DEVICE_ID_OFFSET,
+ OSAL_PCI_READ_CONFIG_WORD(p_dev, RTE_PCI_DEVICE_ID,
&p_dev->device_id);
/* Determine type */
ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
- if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
+ if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
1 << p_hwfn->abs_pf_id / 2);
((u8 *)fw_lsb)[1] = mac[4];
}
+void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
+ char *buf_str, u32 buf_size)
+{
+ u32 len;
+
+ OSAL_SNPRINTF(buf_str, buf_size, "Ecore %d.%d.%d.%d. ",
+ ECORE_MAJOR_VERSION, ECORE_MINOR_VERSION,
+ ECORE_REVISION_VERSION, ECORE_ENGINEERING_VERSION);
+
+ len = OSAL_STRLEN(buf_str);
+ OSAL_SET_PLATFORM_STR(p_hwfn, &buf_str[len], buf_size - len);
+}
+
bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
{
- return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
+ return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
}