net/qede/base: update HSI

[dpdk.git] / drivers / net / qede / base / ecore_init_ops.c

diff --git a/drivers/net/qede/base/ecore_init_ops.c b/drivers/net/qede/base/ecore_init_ops.c
index eadccf4..ad8570a 100644 (file)
--- a/drivers/net/qede/base/ecore_init_ops.c
+++ b/drivers/net/qede/base/ecore_init_ops.c
@@ -1,9 +1,7 @@
-/*
+/* SPDX-License-Identifier: BSD-3-Clause
  * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
  * www.cavium.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
  */
 
 /* include the precompiled configuration values - only once */
@@ -103,7 +101,8 @@ static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
 
                rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
                                         (osal_uintptr_t)(p_init_val + i),
-                                        addr + (i << 2), segment, 0);
+                                        addr + (i << 2), segment,
+                                        OSAL_NULL /* default parameters */);
                if (rc != ECORE_SUCCESS)
                        return rc;
 
@@ -167,8 +166,9 @@ static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
        } else {
                rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
                                         (osal_uintptr_t)(p_buf +
-                                                          dmae_data_offset),
-                                        addr, size, 0);
+                                                         dmae_data_offset),
+                                        addr, size,
+                                        OSAL_NULL /* default parameters */);
        }
 
        return rc;
@@ -179,13 +179,15 @@ static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
                                                 u32 addr, u32 fill_count)
 {
        static u32 zero_buffer[DMAE_MAX_RW_SIZE];
+       struct dmae_params params;
 
        OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
 
+       OSAL_MEMSET(&params, 0, sizeof(params));
+       SET_FIELD(params.flags, DMAE_PARAMS_RW_REPL_SRC, 0x1);
        return ecore_dmae_host2grc(p_hwfn, p_ptt,
                                   (osal_uintptr_t)&zero_buffer[0],
-                                  addr, fill_count,
-                                  ECORE_DMAE_FLAG_RW_REPL_SRC);
+                                  addr, fill_count, &params);
 }
 
 static void ecore_init_fill(struct ecore_hwfn *p_hwfn,
@@ -418,11 +420,11 @@ static u8 ecore_init_cmd_mode_match(struct ecore_hwfn *p_hwfn,
                                    u16 *p_offset, int modes)
 {
        struct ecore_dev *p_dev = p_hwfn->p_dev;
-       const u8 *modes_tree_buf;
        u8 arg1, arg2, tree_val;
+       const u8 *modes_tree;
 
-       modes_tree_buf = p_dev->fw_data->modes_tree_buf;
-       tree_val = modes_tree_buf[(*p_offset)++];
+       modes_tree = p_dev->fw_data->modes_tree_buf;
+       tree_val = modes_tree[(*p_offset)++];
        switch (tree_val) {
        case INIT_MODE_OP_NOT:
                return ecore_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1;
@@ -472,12 +474,12 @@ enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
 {
        struct ecore_dev *p_dev = p_hwfn->p_dev;
        u32 cmd_num, num_init_ops;
-       union init_op *init_ops;
+       union init_op *init;
        bool b_dmae = false;
        enum _ecore_status_t rc = ECORE_SUCCESS;
 
        num_init_ops = p_dev->fw_data->init_ops_size;
-       init_ops = p_dev->fw_data->init_ops;
+       init = p_dev->fw_data->init_ops;
 
 #ifdef CONFIG_ECORE_ZIPPED_FW
        p_hwfn->unzip_buf = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
@@ -489,7 +491,7 @@ enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
 #endif
 
        for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) {
-               union init_op *cmd = &init_ops[cmd_num];
+               union init_op *cmd = &init[cmd_num];
                u32 data = OSAL_LE32_TO_CPU(cmd->raw.op_data);
 
                switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) {
@@ -532,53 +534,6 @@ enum _ecore_status_t ecore_init_run(struct ecore_hwfn *p_hwfn,
        return rc;
 }
 
-void ecore_gtt_init(struct ecore_hwfn *p_hwfn,
-                   struct ecore_ptt *p_ptt)
-{
-       u32 gtt_base;
-       u32 i;
-
-#ifndef ASIC_ONLY
-       if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
-               /* This is done by MFW on ASIC; regardless, this should only
-                * be done once per chip [i.e., common]. Implementation is
-                * not too bright, but it should work on the simple FPGA/EMUL
-                * scenarios.
-                */
-               static bool initialized;
-               int poll_cnt = 500;
-               u32 val;
-
-               /* initialize PTT/GTT (poll for completion) */
-               if (!initialized) {
-                       ecore_wr(p_hwfn, p_ptt,
-                                PGLUE_B_REG_START_INIT_PTT_GTT, 1);
-                       initialized = true;
-               }
-
-               do {
-                       /* ptt might be overrided by HW until this is done */
-                       OSAL_UDELAY(10);
-                       ecore_ptt_invalidate(p_hwfn);
-                       val = ecore_rd(p_hwfn, p_ptt,
-                                      PGLUE_B_REG_INIT_DONE_PTT_GTT);
-               } while ((val != 1) && --poll_cnt);
-
-               if (!poll_cnt)
-                       DP_ERR(p_hwfn,
-                              "PGLUE_B_REG_INIT_DONE didn't complete\n");
-       }
-#endif
-
-       /* Set the global windows */
-       gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START;
-
-       for (i = 0; i < OSAL_ARRAY_SIZE(pxp_global_win); i++)
-               if (pxp_global_win[i])
-                       REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE,
-                              pxp_global_win[i]);
-}
-
 enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
 #ifdef CONFIG_ECORE_BINARY_FW
                                        const u8 *fw_data)