net/ice/base: add GENEVE offset
[dpdk.git] / drivers / net / qede / base / ecore_int.c
index fd8f657..7368d55 100644 (file)
@@ -1224,8 +1224,9 @@ static enum _ecore_status_t ecore_int_attentions(struct ecore_hwfn *p_hwfn)
 static void ecore_sb_ack_attn(struct ecore_hwfn *p_hwfn,
                              void OSAL_IOMEM *igu_addr, u32 ack_cons)
 {
-       struct igu_prod_cons_update igu_ack = { 0 };
+       struct igu_prod_cons_update igu_ack;
 
+       OSAL_MEMSET(&igu_ack, 0, sizeof(struct igu_prod_cons_update));
        igu_ack.sb_id_and_flags =
            ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
             (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
@@ -1561,11 +1562,13 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
                ecore_dmae_host2grc(p_hwfn, p_ptt,
                                    (u64)(osal_uintptr_t)&phys_addr,
                                    CAU_REG_SB_ADDR_MEMORY +
-                                   igu_sb_id * sizeof(u64), 2, 0);
+                                   igu_sb_id * sizeof(u64), 2,
+                                   OSAL_NULL /* default parameters */);
                ecore_dmae_host2grc(p_hwfn, p_ptt,
                                    (u64)(osal_uintptr_t)&sb_entry,
                                    CAU_REG_SB_VAR_MEMORY +
-                                   igu_sb_id * sizeof(u64), 2, 0);
+                                   igu_sb_id * sizeof(u64), 2,
+                                   OSAL_NULL /* default parameters */);
        } else {
                /* Initialize Status Block Address */
                STORE_RT_REG_AGG(p_hwfn,
@@ -2646,7 +2649,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
 
        rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
                                 sb_id * sizeof(u64),
-                                (u64)(osal_uintptr_t)&sb_entry, 2, 0);
+                                (u64)(osal_uintptr_t)&sb_entry, 2,
+                                OSAL_NULL /* default parameters */);
        if (rc != ECORE_SUCCESS) {
                DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
                return rc;
@@ -2659,8 +2663,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
 
        rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
                                 (u64)(osal_uintptr_t)&sb_entry,
-                                CAU_REG_SB_VAR_MEMORY +
-                                sb_id * sizeof(u64), 2, 0);
+                                CAU_REG_SB_VAR_MEMORY + sb_id * sizeof(u64), 2,
+                                OSAL_NULL /* default parameters */);
        if (rc != ECORE_SUCCESS) {
                DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
                return rc;