net/qede/base: enable control frame filtering

[dpdk.git] / drivers / net / qede / base / ecore_l2.c

diff --git a/drivers/net/qede/base/ecore_l2.c b/drivers/net/qede/base/ecore_l2.c
index 91d89e5..c17082e 100644 (file)
--- a/drivers/net/qede/base/ecore_l2.c
+++ b/drivers/net/qede/base/ecore_l2.c
@@ -1,9 +1,7 @@
-/*
+/* SPDX-License-Identifier: BSD-3-Clause
  * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
  * www.cavium.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
  */
 
 #include "bcm_osal.h"
@@ -610,6 +608,9 @@ ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
                SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
                          !!(accept_filter & ECORE_ACCEPT_BCAST));
 
+               SET_FIELD(state, ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI,
+                         !!(accept_filter & ECORE_ACCEPT_ANY_VNI));
+
                p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
                DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
                           "vport[%02x] p_ramrod->rx_mode.state = 0x%x\n",
@@ -785,6 +786,11 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
                return rc;
        }
 
+       if (p_params->update_ctl_frame_check) {
+               p_cmn->ctl_frame_mac_check_en = p_params->mac_chk_en;
+               p_cmn->ctl_frame_ethtype_check_en = p_params->ethtype_chk_en;
+       }
+
        /* Update mcast bins for VFs, PF doesn't use this functionality */
        ecore_sp_update_mcast_bin(p_ramrod, p_params);
 
@@ -2086,6 +2092,24 @@ void ecore_reset_vport_stats(struct ecore_dev *p_dev)
        }
 }
 
+static enum gft_profile_type
+ecore_arfs_mode_to_hsi(enum ecore_filter_config_mode mode)
+{
+       if (mode == ECORE_FILTER_CONFIG_MODE_5_TUPLE)
+               return GFT_PROFILE_TYPE_4_TUPLE;
+
+       if (mode == ECORE_FILTER_CONFIG_MODE_IP_DEST)
+               return GFT_PROFILE_TYPE_IP_DST_ADDR;
+
+       if (mode == ECORE_FILTER_CONFIG_MODE_TUNN_TYPE)
+               return GFT_PROFILE_TYPE_TUNNEL_TYPE;
+
+       if (mode == ECORE_FILTER_CONFIG_MODE_IP_SRC)
+               return GFT_PROFILE_TYPE_IP_SRC_ADDR;
+
+       return GFT_PROFILE_TYPE_L4_DST_PORT;
+}
+
 void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
                               struct ecore_ptt *p_ptt,
                               struct ecore_arfs_config_params *p_cfg_params)
@@ -2093,13 +2117,13 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
        if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))
                return;
 
-       if (p_cfg_params->arfs_enable) {
+       if (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) {
                ecore_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
                                 p_cfg_params->tcp,
                                 p_cfg_params->udp,
                                 p_cfg_params->ipv4,
                                 p_cfg_params->ipv6,
-                                GFT_PROFILE_TYPE_4_TUPLE);
+                                ecore_arfs_mode_to_hsi(p_cfg_params->mode));
                DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
                           "tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
                           p_cfg_params->tcp ? "Enable" : "Disable",
@@ -2109,8 +2133,8 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
        } else {
                ecore_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
        }
-       DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
-                  p_cfg_params->arfs_enable ? "Enable" : "Disable");
+       DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %d\n",
+                  (int)p_cfg_params->mode);
 }
 
 enum _ecore_status_t
@@ -2304,3 +2328,55 @@ ecore_eth_tx_queue_maxrate(struct ecore_hwfn *p_hwfn,
        return ecore_init_vport_rl(p_hwfn, p_ptt, vport, rate,
                                   p_link->speed);
 }
+
+#define RSS_TSTORM_UPDATE_STATUS_MAX_POLL_COUNT    100
+#define RSS_TSTORM_UPDATE_STATUS_POLL_PERIOD_US    1
+
+enum _ecore_status_t
+ecore_update_eth_rss_ind_table_entry(struct ecore_hwfn *p_hwfn,
+                                    u8 vport_id,
+                                    u8 ind_table_index,
+                                    u16 ind_table_value)
+{
+       struct eth_tstorm_rss_update_data update_data = { 0 };
+       void OSAL_IOMEM *addr = OSAL_NULL;
+       enum _ecore_status_t rc;
+       u8 abs_vport_id;
+       u32 cnt = 0;
+
+       OSAL_BUILD_BUG_ON(sizeof(update_data) != sizeof(u64));
+
+       rc = ecore_fw_vport(p_hwfn, vport_id, &abs_vport_id);
+       if (rc != ECORE_SUCCESS)
+               return rc;
+
+       addr = (u8 OSAL_IOMEM *)p_hwfn->regview +
+              GTT_BAR0_MAP_REG_TSDM_RAM +
+              TSTORM_ETH_RSS_UPDATE_OFFSET(p_hwfn->rel_pf_id);
+
+       *(u64 *)(&update_data) = DIRECT_REG_RD64(p_hwfn, addr);
+
+       for (cnt = 0; update_data.valid &&
+            cnt < RSS_TSTORM_UPDATE_STATUS_MAX_POLL_COUNT; cnt++) {
+               OSAL_UDELAY(RSS_TSTORM_UPDATE_STATUS_POLL_PERIOD_US);
+               *(u64 *)(&update_data) = DIRECT_REG_RD64(p_hwfn, addr);
+       }
+
+       if (update_data.valid) {
+               DP_NOTICE(p_hwfn, true,
+                         "rss update valid status is not clear! valid=0x%x vport id=%d ind_Table_idx=%d ind_table_value=%d.\n",
+                         update_data.valid, vport_id, ind_table_index,
+                         ind_table_value);
+
+               return ECORE_AGAIN;
+       }
+
+       update_data.valid           = 1;
+       update_data.ind_table_index = ind_table_index;
+       update_data.ind_table_value = ind_table_value;
+       update_data.vport_id        = abs_vport_id;
+
+       DIRECT_REG_WR64(p_hwfn, addr, *(u64 *)(&update_data));
+
+       return ECORE_SUCCESS;
+}