mempool: introduce helpers for populate and required size

[dpdk.git] / drivers / net / qede / base / ecore_mcp.h

diff --git a/drivers/net/qede/base/ecore_mcp.h b/drivers/net/qede/base/ecore_mcp.h
index 7f12a0a..185cc23 100644 (file)
--- a/drivers/net/qede/base/ecore_mcp.h
+++ b/drivers/net/qede/base/ecore_mcp.h
@@ -1,9 +1,7 @@
-/*
- * Copyright (c) 2016 QLogic Corporation.
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright (c) 2016 - 2018 Cavium Inc.
  * All rights reserved.
- * www.qlogic.com
- *
- * See LICENSE.qede_pmd for copyright and licensing details.
+ * www.cavium.com
  */
 
 #ifndef __ECORE_MCP_H__
@@ -27,9 +25,6 @@
                                             rel_pfid)
 #define MCP_PF_ID(p_hwfn)      MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id)
 
-#define MFW_PORT(_p_hwfn)      ((_p_hwfn)->abs_pf_id % \
-                                ecore_device_num_ports((_p_hwfn)->p_dev))
-
 struct ecore_mcp_info {
        /* List for mailbox commands which were sent and wait for a response */
        osal_list_t cmd_list;
@@ -80,11 +75,16 @@ struct ecore_mcp_mb_params {
        u32 cmd;
        u32 param;
        void *p_data_src;
-       u8 data_src_size;
        void *p_data_dst;
-       u8 data_dst_size;
        u32 mcp_resp;
        u32 mcp_param;
+       u8 data_src_size;
+       u8 data_dst_size;
+       u32 flags;
+#define ECORE_MB_FLAG_CAN_SLEEP         (0x1 << 0)
+#define ECORE_MB_FLAG_AVOID_BLOCK       (0x1 << 1)
+#define ECORE_MB_FLAGS_IS_SET(params, flag) \
+       ((params) != OSAL_NULL && ((params)->flags & ECORE_MB_FLAG_##flag))
 };
 
 struct ecore_drv_tlv_hdr {
@@ -521,6 +521,41 @@ enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
                                                struct ecore_ptt *p_ptt);
 
+enum ecore_mcp_drv_attr_cmd {
+       ECORE_MCP_DRV_ATTR_CMD_READ,
+       ECORE_MCP_DRV_ATTR_CMD_WRITE,
+       ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR,
+       ECORE_MCP_DRV_ATTR_CMD_CLEAR,
+};
+
+struct ecore_mcp_drv_attr {
+       enum ecore_mcp_drv_attr_cmd attr_cmd;
+       u32 attr_num;
+
+       /* R/RC - will be set with the read value
+        * W - should hold the required value to be written
+        * C - DC
+        */
+       u32 val;
+
+       /* W - mask/offset to be applied on the given value
+        * R/RC/C - DC
+        */
+       u32 mask;
+       u32 offset;
+};
+
+/**
+ * @brief Handle the drivers' attributes that are kept by the MFW.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ * @param p_drv_attr
+ */
+enum _ecore_status_t
+ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
+                       struct ecore_mcp_drv_attr *p_drv_attr);
+
 /**
  * @brief Read ufp config from the shared memory.
  *
@@ -530,4 +565,25 @@ enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
 void
 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
 
+void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
+                     u32 offset, u32 val);
+
+/**
+ * @brief Get the engine affinity configuration.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ */
+enum _ecore_status_t ecore_mcp_get_engine_config(struct ecore_hwfn *p_hwfn,
+                                                struct ecore_ptt *p_ptt);
+
+/**
+ * @brief Get the PPFID bitmap.
+ *
+ * @param p_hwfn
+ * @param p_ptt
+ */
+enum _ecore_status_t ecore_mcp_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
+                                               struct ecore_ptt *p_ptt);
+
 #endif /* __ECORE_MCP_H__ */