net/virtio: add parameter to enable vectorized path

[dpdk.git] / drivers / net / qede / base / ecore_sp_commands.c

diff --git a/drivers/net/qede/base/ecore_sp_commands.c b/drivers/net/qede/base/ecore_sp_commands.c
index b43baf9..9860a62 100644 (file)
--- a/drivers/net/qede/base/ecore_sp_commands.c
+++ b/drivers/net/qede/base/ecore_sp_commands.c
@@ -355,14 +355,16 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
                p_ramrod->outer_tag_config.inner_to_outer_pri_map[i] = i;
 
        /* enable_stag_pri_change should be set if port is in BD mode or,
-        * UFP with Host Control mode or, UFP with DCB over base interface.
+        * UFP with Host Control mode.
         */
        if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
-               if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
-                   (p_hwfn->p_dcbx_info->results.dcbx_enabled))
+               if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)
                        p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
                else
                        p_ramrod->outer_tag_config.enable_stag_pri_change = 0;
+
+               p_ramrod->outer_tag_config.outer_tag.tci |=
+                       OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));
        }
 
        /* Place EQ address in RAMROD */
@@ -459,8 +461,7 @@ enum _ecore_status_t ecore_sp_pf_update_ufp(struct ecore_hwfn *p_hwfn)
                return rc;
 
        p_ent->ramrod.pf_update.update_enable_stag_pri_change = true;
-       if ((p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS) ||
-           (p_hwfn->p_dcbx_info->results.dcbx_enabled))
+       if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)
                p_ent->ramrod.pf_update.enable_stag_pri_change = 1;
        else
                p_ent->ramrod.pf_update.enable_stag_pri_change = 0;
@@ -515,6 +516,10 @@ enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
        rl_update->rl_id_first = params->rl_id_first;
        rl_update->rl_id_last = params->rl_id_last;
        rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
+       rl_update->dcqcn_reset_alpha_on_idle =
+               params->dcqcn_reset_alpha_on_idle;
+       rl_update->rl_bc_stage_th = params->rl_bc_stage_th;
+       rl_update->rl_timer_stage_th = params->rl_timer_stage_th;
        rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
        rl_update->rl_max_rate =
                OSAL_CPU_TO_LE16(ecore_sp_rl_mb_to_qm(params->rl_max_rate));
@@ -529,12 +534,14 @@ enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
                OSAL_CPU_TO_LE32(params->dcqcn_timeuot_us);
        rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
 
-       DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
+       DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ, "rl_params: qcn_update_param_flg %x, dcqcn_update_param_flg %x, rl_init_flg %x, rl_start_flg %x, rl_stop_flg %x, rl_id_first %x, rl_id_last %x, rl_dc_qcn_flg %x,dcqcn_reset_alpha_on_idle %x, rl_bc_stage_th %x, rl_timer_stage_th %x, rl_bc_rate %x, rl_max_rate %x, rl_r_ai %x, rl_r_hai %x, dcqcn_g %x, dcqcn_k_us %x, dcqcn_timeuot_us %x, qcn_timeuot_us %x\n",
                   rl_update->qcn_update_param_flg,
                   rl_update->dcqcn_update_param_flg,
                   rl_update->rl_init_flg, rl_update->rl_start_flg,
                   rl_update->rl_stop_flg, rl_update->rl_id_first,
                   rl_update->rl_id_last, rl_update->rl_dc_qcn_flg,
+                  rl_update->dcqcn_reset_alpha_on_idle,
+                  rl_update->rl_bc_stage_th, rl_update->rl_timer_stage_th,
                   rl_update->rl_bc_rate, rl_update->rl_max_rate,
                   rl_update->rl_r_ai, rl_update->rl_r_hai,
                   rl_update->dcqcn_g, rl_update->dcqcn_k_us,
@@ -631,6 +638,10 @@ enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
        if (rc != ECORE_SUCCESS)
                return rc;
 
+       if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
+               p_ent->ramrod.pf_update.mf_vlan |=
+                       OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));
+
        return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
 }