#include <rte_ether.h>
#include <rte_ethdev.h>
+#include <rte_ethdev_pci.h>
#include <rte_dev.h>
#include <rte_ip.h>
#include "base/nvm_cfg.h"
#include "base/ecore_iov_api.h"
#include "base/ecore_sp_commands.h"
+#include "base/ecore_l2.h"
+#include "base/ecore_dev_api.h"
#include "qede_logs.h"
#include "qede_if.h"
/* Driver versions */
#define QEDE_PMD_VER_PREFIX "QEDE PMD"
-#define QEDE_PMD_VERSION_MAJOR 1
-#define QEDE_PMD_VERSION_MINOR 2
+#define QEDE_PMD_VERSION_MAJOR 2
+#define QEDE_PMD_VERSION_MINOR 4
#define QEDE_PMD_VERSION_REVISION 0
#define QEDE_PMD_VERSION_PATCH 1
#define CHIP_NUM_57980S_25 0x1656
#define CHIP_NUM_57980S_IOV 0x1664
#define CHIP_NUM_57980S_100 0x1644
+#define CHIP_NUM_57980S_50 0x1654
#define CHIP_NUM_AH_50G 0x8070
#define CHIP_NUM_AH_10G 0x8071
#define CHIP_NUM_AH_40G 0x8072
#define PCI_DEVICE_ID_QLOGIC_57980S_25 CHIP_NUM_57980S_25
#define PCI_DEVICE_ID_QLOGIC_57980S_IOV CHIP_NUM_57980S_IOV
#define PCI_DEVICE_ID_QLOGIC_57980S_100 CHIP_NUM_57980S_100
+#define PCI_DEVICE_ID_QLOGIC_57980S_50 CHIP_NUM_57980S_50
#define PCI_DEVICE_ID_QLOGIC_AH_50G CHIP_NUM_AH_50G
#define PCI_DEVICE_ID_QLOGIC_AH_10G CHIP_NUM_AH_10G
#define PCI_DEVICE_ID_QLOGIC_AH_40G CHIP_NUM_AH_40G
/* Number of PF connections - 32 RX + 32 TX */
#define QEDE_PF_NUM_CONNS (64)
+/* Maximum number of flowdir filters */
+#define QEDE_RFS_MAX_FLTR (256)
+
/* Port/function states */
enum qede_dev_state {
QEDE_DEV_INIT, /* Init the chip and Slowpath */
SLIST_ENTRY(qede_ucast_entry) list;
};
+struct qede_fdir_entry {
+ uint32_t soft_id; /* unused for now */
+ uint16_t pkt_len; /* actual packet length to match */
+ uint16_t rx_queue; /* queue to be steered to */
+ const struct rte_memzone *mz; /* mz used to hold L2 frame */
+ SLIST_ENTRY(qede_fdir_entry) list;
+};
+
+struct qede_fdir_info {
+ struct ecore_arfs_config_params arfs;
+ uint16_t filter_count;
+ SLIST_HEAD(fdir_list_head, qede_fdir_entry)fdir_list_head;
+};
+
+
/*
* Structure to store private data for each port.
*/
uint16_t rss_ind_table[ECORE_RSS_IND_TABLE_SIZE];
uint64_t rss_hf;
uint8_t rss_key_len;
- uint32_t flags;
- bool gro_disable;
+ bool enable_lro;
uint16_t num_queues;
uint8_t fp_num_tx;
uint8_t fp_num_rx;
bool handle_hw_err;
uint16_t num_tunn_filters;
uint16_t vxlan_filter_type;
+ struct qede_fdir_info fdir_info;
char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
};
static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags);
+static uint16_t qede_fdir_construct_pkt(struct rte_eth_dev *eth_dev,
+ struct rte_eth_fdir_filter *fdir,
+ void *buff,
+ struct ecore_arfs_config_params *param);
+
/* Non-static functions */
-void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf);
+int qede_config_rss(struct rte_eth_dev *eth_dev);
int qed_fill_eth_dev_info(struct ecore_dev *edev,
struct qed_dev_eth_info *info);
int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up);
+int qede_dev_filter_ctrl(struct rte_eth_dev *dev, enum rte_filter_type type,
+ enum rte_filter_op op, void *arg);
+
+int qede_fdir_filter_conf(struct rte_eth_dev *eth_dev,
+ enum rte_filter_op filter_op, void *arg);
+
+int qede_ntuple_filter_conf(struct rte_eth_dev *eth_dev,
+ enum rte_filter_op filter_op, void *arg);
+
+int qede_check_fdir_support(struct rte_eth_dev *eth_dev);
+
+void qede_fdir_dealloc_resc(struct rte_eth_dev *eth_dev);
+
#endif /* _QEDE_ETHDEV_H_ */