net/liquidio: add Tx data path for multiple segments

[dpdk.git] / drivers / net / qede / qede_rxtx.h

diff --git a/drivers/net/qede/qede_rxtx.h b/drivers/net/qede/qede_rxtx.h
index 3e1e977..9a393e9 100644 (file)
--- a/drivers/net/qede/qede_rxtx.h
+++ b/drivers/net/qede/qede_rxtx.h
@@ -41,10 +41,6 @@
                (bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
                (bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
                (bd)->nbytes = rte_cpu_to_le_16(len); \
-               /* FW 8.10.x specific change */  \
-               (bd)->data.bitfields = ((len) & \
-                                        ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) \
-                                       << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; \
        } while (0)
 
 #define CQE_HAS_VLAN(flags) \
@@ -55,18 +51,29 @@
        ((flags) & (PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK \
                << PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT))
 
+#define QEDE_MIN_RX_BUFF_SIZE          (1024)
+#define QEDE_VLAN_TAG_SIZE             (4)
+#define QEDE_LLC_SNAP_HDR_LEN          (8)
+
 /* Max supported alignment is 256 (8 shift)
  * minimal alignment shift 6 is optimal for 57xxx HW performance
  */
 #define QEDE_L1_CACHE_SHIFT    6
 #define QEDE_RX_ALIGN_SHIFT    (RTE_MAX(6, RTE_MIN(8, QEDE_L1_CACHE_SHIFT)))
 #define QEDE_FW_RX_ALIGN_END   (1UL << QEDE_RX_ALIGN_SHIFT)
-
-#define QEDE_ETH_OVERHEAD       (ETHER_HDR_LEN + 8 + 8 + QEDE_FW_RX_ALIGN_END)
-
-/* TBD: Excluding IPV6 */
-#define QEDE_RSS_OFFLOAD_ALL    (ETH_RSS_IPV4 | ETH_RSS_NONFRAG_IPV4_TCP | \
-                                ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_VXLAN)
+#define QEDE_CEIL_TO_CACHE_LINE_SIZE(n) (((n) + (QEDE_FW_RX_ALIGN_END - 1)) & \
+                                       ~(QEDE_FW_RX_ALIGN_END - 1))
+/* Note: QEDE_LLC_SNAP_HDR_LEN is optional */
+#define QEDE_ETH_OVERHEAD      ((ETHER_HDR_LEN) + ((2 * QEDE_VLAN_TAG_SIZE)) \
+                               + (QEDE_LLC_SNAP_HDR_LEN))
+
+#define QEDE_RSS_OFFLOAD_ALL    (ETH_RSS_IPV4                  |\
+                                ETH_RSS_NONFRAG_IPV4_TCP       |\
+                                ETH_RSS_NONFRAG_IPV4_UDP       |\
+                                ETH_RSS_IPV6                   |\
+                                ETH_RSS_NONFRAG_IPV6_TCP       |\
+                                ETH_RSS_NONFRAG_IPV6_UDP       |\
+                                ETH_RSS_VXLAN)
 
 #define QEDE_TXQ_FLAGS         ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS)