-/*
- * Copyright (c) 2012-2016 Solarflare Communications Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
+/* SPDX-License-Identifier: BSD-3-Clause
*
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * The views and conclusions contained in the software and documentation are
- * those of the authors and should not be interpreted as representing official
- * policies, either expressed or implied, of the FreeBSD Project.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2012-2019 Solarflare Communications Inc.
*/
#include "efx.h"
#include "efx_impl.h"
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFX_OPTS_EF10()
#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
if (tlv_tag(cursor) != TLV_TAG_END) {
/* Check current item has space for tag and length */
- if (cursor->current > (cursor->limit - 2)) {
+ if (cursor->current > (cursor->limit - 1)) {
cursor->current = NULL;
rc = EFAULT;
goto fail3;
}
- /* Check we have value data for current item and another tag */
- if (tlv_next_item_ptr(cursor) > (cursor->limit - 1)) {
+ /* Check we have value data for current item and an END tag */
+ if (tlv_next_item_ptr(cursor) > cursor->limit) {
cursor->current = NULL;
rc = EFAULT;
goto fail4;
if (len > 0) {
ptr[(len - 1) / sizeof (uint32_t)] = 0;
memcpy(ptr, data, len);
- ptr += P2ROUNDUP(len, sizeof (uint32_t)) / sizeof (*ptr);
+ ptr += EFX_P2ROUNDUP(uint32_t, len,
+ sizeof (uint32_t)) / sizeof (*ptr);
}
return (ptr);
/* Validate buffer contents (before writing to flash) */
__checkReturn efx_rc_t
ef10_nvram_buffer_validate(
- __in efx_nic_t *enp,
__in uint32_t partn,
__in_bcount(partn_size) caddr_t partn_data,
__in size_t partn_size)
goto fail4;
}
+ /* Check partition header matches partn */
+ if (__LE_TO_CPU_16(header->type_id) != partn) {
+ rc = EINVAL;
+ goto fail5;
+ }
+
/* Check partition ends with PARTITION_TRAILER and END tags */
if ((rc = tlv_find(&cursor, TLV_TAG_PARTITION_TRAILER)) != 0) {
rc = EINVAL;
- goto fail5;
+ goto fail6;
}
trailer = (struct tlv_partition_trailer *)tlv_item(&cursor);
if ((rc = tlv_advance(&cursor)) != 0) {
rc = EINVAL;
- goto fail6;
+ goto fail7;
}
if (tlv_tag(&cursor) != TLV_TAG_END) {
rc = EINVAL;
- goto fail7;
+ goto fail8;
}
/* Check generation counts are consistent */
if (trailer->generation != header->generation) {
rc = EINVAL;
- goto fail8;
+ goto fail9;
}
/* Verify partition checksum */
}
if (cksum != 0) {
rc = EINVAL;
- goto fail9;
+ goto fail10;
}
return (0);
+fail10:
+ EFSYS_PROBE(fail10);
fail9:
EFSYS_PROBE(fail9);
fail8:
return (rc);
}
+ void
+ef10_nvram_buffer_init(
+ __out_bcount(buffer_size)
+ caddr_t bufferp,
+ __in size_t buffer_size)
+{
+ uint32_t *buf = (uint32_t *)bufferp;
+ memset(buf, 0xff, buffer_size);
+
+ tlv_init_block(buf);
+}
__checkReturn efx_rc_t
ef10_nvram_buffer_create(
- __in efx_nic_t *enp,
- __in uint16_t partn_type,
- __in_bcount(partn_size) caddr_t partn_data,
+ __in uint32_t partn_type,
+ __out_bcount(partn_size)
+ caddr_t partn_data,
__in size_t partn_size)
{
uint32_t *buf = (uint32_t *)partn_data;
goto fail1;
}
- memset(buf, 0xff, partn_size);
+ ef10_nvram_buffer_init(partn_data, partn_size);
- tlv_init_block(buf);
if ((rc = tlv_init_cursor(&cursor, buf,
(uint32_t *)((uint8_t *)buf + partn_size),
buf)) != 0) {
goto fail6;
/* Check that the partition is valid. */
- if ((rc = ef10_nvram_buffer_validate(enp, partn_type,
+ if ((rc = ef10_nvram_buffer_validate(partn_type,
partn_data, partn_size)) != 0)
goto fail7;
return (B_FALSE);
}
+ __checkReturn efx_rc_t
+ef10_nvram_buffer_peek_item(
+ __in_bcount(buffer_size)
+ caddr_t bufferp,
+ __in size_t buffer_size,
+ __in uint32_t offset,
+ __out uint32_t *tagp,
+ __out uint32_t *lengthp,
+ __out uint32_t *value_offsetp)
+{
+ efx_rc_t rc;
+ tlv_cursor_t cursor;
+ uint32_t tag;
+
+ if ((rc = tlv_init_cursor_at_offset(&cursor, (uint8_t *)bufferp,
+ buffer_size, offset)) != 0) {
+ goto fail1;
+ }
+
+ tag = tlv_tag(&cursor);
+ *tagp = tag;
+ if (tag == TLV_TAG_END) {
+ /*
+ * To allow stepping over the END tag, report the full tag
+ * length and a zero length value.
+ */
+ *lengthp = sizeof (tag);
+ *value_offsetp = sizeof (tag);
+ } else {
+ *lengthp = byte_offset(tlv_next_item_ptr(&cursor),
+ cursor.current);
+ *value_offsetp = byte_offset((uint32_t *)tlv_value(&cursor),
+ cursor.current);
+ }
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
__checkReturn efx_rc_t
ef10_nvram_buffer_get_item(
__in_bcount(buffer_size)
__in size_t buffer_size,
__in uint32_t offset,
__in uint32_t length,
- __out_bcount_part(item_max_size, *lengthp)
- caddr_t itemp,
- __in size_t item_max_size,
+ __out uint32_t *tagp,
+ __out_bcount_part(value_max_size, *lengthp)
+ caddr_t valuep,
+ __in size_t value_max_size,
__out uint32_t *lengthp)
{
efx_rc_t rc;
tlv_cursor_t cursor;
- uint32_t item_length;
+ uint32_t value_length;
- if (item_max_size < length) {
+ if (buffer_size < (offset + length)) {
rc = ENOSPC;
goto fail1;
}
goto fail2;
}
- item_length = tlv_length(&cursor);
- if (length < item_length) {
+ value_length = tlv_length(&cursor);
+ if (value_max_size < value_length) {
rc = ENOSPC;
goto fail3;
}
- memcpy(itemp, tlv_value(&cursor), item_length);
+ memcpy(valuep, tlv_value(&cursor), value_length);
- *lengthp = item_length;
+ *tagp = tlv_tag(&cursor);
+ *lengthp = value_length;
return (0);
caddr_t bufferp,
__in size_t buffer_size,
__in uint32_t offset,
- __in_bcount(length) caddr_t keyp,
+ __in uint32_t tag,
+ __in_bcount(length) caddr_t valuep,
+ __in uint32_t length,
+ __out uint32_t *lengthp)
+{
+ efx_rc_t rc;
+ tlv_cursor_t cursor;
+
+ if ((rc = tlv_init_cursor_at_offset(&cursor, (uint8_t *)bufferp,
+ buffer_size, offset)) != 0) {
+ goto fail1;
+ }
+
+ rc = tlv_insert(&cursor, tag, (uint8_t *)valuep, length);
+
+ if (rc != 0)
+ goto fail2;
+
+ *lengthp = byte_offset(tlv_next_item_ptr(&cursor),
+ cursor.current);
+
+ return (0);
+
+fail2:
+ EFSYS_PROBE(fail2);
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+ef10_nvram_buffer_modify_item(
+ __in_bcount(buffer_size)
+ caddr_t bufferp,
+ __in size_t buffer_size,
+ __in uint32_t offset,
+ __in uint32_t tag,
+ __in_bcount(length) caddr_t valuep,
__in uint32_t length,
__out uint32_t *lengthp)
{
goto fail1;
}
- rc = tlv_insert(&cursor, TLV_TAG_LICENSE, (uint8_t *)keyp, length);
+ rc = tlv_modify(&cursor, tag, (uint8_t *)valuep, length);
if (rc != 0) {
goto fail2;
return (rc);
}
+
__checkReturn efx_rc_t
ef10_nvram_buffer_delete_item(
__in_bcount(buffer_size)
caddr_t value;
efx_rc_t rc;
+ _NOTE(ARGUNUSED(enp))
+
if ((seg_data == NULL) || (max_seg_size == 0)) {
rc = EINVAL;
goto fail1;
*/
retry = 10;
do {
- rc = ef10_nvram_read_tlv_segment(enp, partn, 0,
- seg_data, partn_size);
- } while ((rc == EAGAIN) && (--retry > 0));
+ if ((rc = ef10_nvram_read_tlv_segment(enp, partn, 0,
+ seg_data, partn_size)) != 0)
+ --retry;
+ } while ((rc == EAGAIN) && (retry > 0));
if (rc != 0) {
/* Failed to obtain consistent segment data */
+ if (rc == EAGAIN)
+ rc = EIO;
+
goto fail4;
}
goto fail7;
/* Unlock the partition */
- ef10_nvram_partn_unlock(enp, partn, NULL);
+ (void) ef10_nvram_partn_unlock(enp, partn, NULL);
EFSYS_KMEM_FREE(enp->en_esip, partn_size, partn_data);
fail4:
EFSYS_PROBE(fail4);
- ef10_nvram_partn_unlock(enp, partn, NULL);
+ (void) ef10_nvram_partn_unlock(enp, partn, NULL);
fail3:
EFSYS_PROBE(fail3);
__out size_t *sizep)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
- if ((rc = efx_mcdi_nvram_info(enp, partn, sizep,
- NULL, NULL, NULL)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ *sizep = eni.eni_partn_size;
+
return (0);
fail1:
return (rc);
}
+ __checkReturn efx_rc_t
+ef10_nvram_partn_info(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __out efx_nvram_info_t *enip)
+{
+ efx_rc_t rc;
+
+ if ((rc = efx_mcdi_nvram_info(enp, partn, enip)) != 0)
+ goto fail1;
+
+ if (enip->eni_write_size == 0)
+ enip->eni_write_size = EF10_NVRAM_CHUNK;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+
__checkReturn efx_rc_t
ef10_nvram_partn_lock(
__in efx_nic_t *enp,
__in size_t size)
{
/*
- * Read requests which come in through the EFX API expect to
- * read the current, active partition.
+ * An A/B partition has two data stores (current and backup).
+ * Read requests which come in through the EFX API expect to read the
+ * current, active store of an A/B partition. For non A/B partitions,
+ * there is only a single store and so the mode param is ignored.
*/
return ef10_nvram_partn_read_mode(enp, partn, offset, data, size,
MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT);
}
+ __checkReturn efx_rc_t
+ef10_nvram_partn_read_backup(
+ __in efx_nic_t *enp,
+ __in uint32_t partn,
+ __in unsigned int offset,
+ __out_bcount(size) caddr_t data,
+ __in size_t size)
+{
+ /*
+ * An A/B partition has two data stores (current and backup).
+ * Read the backup store of an A/B partition (i.e. the store currently
+ * being written to if the partition is locked).
+ *
+ * This is needed when comparing the existing partition content to avoid
+ * unnecessary writes, or to read back what has been written to check
+ * that the writes have succeeded.
+ */
+ return ef10_nvram_partn_read_mode(enp, partn, offset, data, size,
+ MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP);
+}
+
__checkReturn efx_rc_t
ef10_nvram_partn_erase(
__in efx_nic_t *enp,
__in size_t size)
{
efx_rc_t rc;
+ efx_nvram_info_t eni = { 0 };
uint32_t erase_size;
- if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,
- &erase_size, NULL)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ erase_size = eni.eni_erase_size;
+
if (erase_size == 0) {
if ((rc = efx_mcdi_nvram_erase(enp, partn, offset, size)) != 0)
goto fail2;
__in efx_nic_t *enp,
__in uint32_t partn,
__in unsigned int offset,
- __out_bcount(size) caddr_t data,
+ __in_bcount(size) caddr_t data,
__in size_t size)
{
size_t chunk;
+ efx_nvram_info_t eni = { 0 };
uint32_t write_size;
efx_rc_t rc;
- if ((rc = efx_mcdi_nvram_info(enp, partn, NULL, NULL,
- NULL, &write_size)) != 0)
+ if ((rc = efx_mcdi_nvram_info(enp, partn, &eni)) != 0)
goto fail1;
+ write_size = eni.eni_write_size;
+
if (write_size != 0) {
/*
* Check that the size is a multiple of the write chunk size if
return (rc);
}
+#define EF10_NVRAM_INITIAL_POLL_DELAY_US 10000
+#define EF10_NVRAM_MAX_POLL_DELAY_US 1000000
+#define EF10_NVRAM_POLL_RETRIES 100
+
__checkReturn efx_rc_t
ef10_nvram_partn_unlock(
__in efx_nic_t *enp,
__in uint32_t partn,
- __out_opt uint32_t *resultp)
+ __out_opt uint32_t *verify_resultp)
{
boolean_t reboot = B_FALSE;
+ uint32_t poll_delay_us = EF10_NVRAM_INITIAL_POLL_DELAY_US;
+ uint32_t poll_retry = 0;
+ uint32_t verify_result = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
efx_rc_t rc;
- if (resultp != NULL)
- *resultp = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
+ rc = efx_mcdi_nvram_update_finish(enp, partn, reboot,
+ EFX_NVRAM_UPDATE_FLAGS_BACKGROUND, &verify_result);
- rc = efx_mcdi_nvram_update_finish(enp, partn, reboot, resultp);
- if (rc != 0)
- goto fail1;
+ /*
+ * NVRAM updates can take a long time (e.g. up to 1 minute for bundle
+ * images). Polling for NVRAM update completion ensures that other MCDI
+ * commands can be issued before the background NVRAM update completes.
+ *
+ * Without polling, other MCDI commands can only be issued before the
+ * NVRAM update completes if the MCDI transport and the firmware
+ * support the Asynchronous MCDI protocol extensions in SF-116575-PS.
+ *
+ * The initial call either completes the update synchronously, or
+ * returns RC_PENDING to indicate processing is continuing. In the
+ * latter case, we poll for at least 1 minute, at increasing intervals
+ * (10ms, 100ms, 1s).
+ */
+ while (verify_result == MC_CMD_NVRAM_VERIFY_RC_PENDING) {
+
+ if (poll_retry > EF10_NVRAM_POLL_RETRIES) {
+ rc = ETIMEDOUT;
+ goto fail1;
+ }
+ poll_retry++;
+
+ EFSYS_SLEEP(poll_delay_us);
+ if (poll_delay_us < EF10_NVRAM_MAX_POLL_DELAY_US)
+ poll_delay_us *= 10;
+
+ /* Poll for completion of background NVRAM update. */
+ verify_result = MC_CMD_NVRAM_VERIFY_RC_UNKNOWN;
+
+ rc = efx_mcdi_nvram_update_finish(enp, partn, reboot,
+ EFX_NVRAM_UPDATE_FLAGS_POLL, &verify_result);
+ if (rc != 0) {
+ /* Poll failed, so assume NVRAM update failed. */
+ goto fail2;
+ }
+ }
+
+ if (verify_resultp != NULL)
+ *verify_resultp = verify_result;
return (0);
+fail2:
+ EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
typedef struct ef10_parttbl_entry_s {
unsigned int partn;
- unsigned int port;
+ unsigned int port_mask;
efx_nvram_type_t nvtype;
} ef10_parttbl_entry_t;
+/* Port mask values */
+#define PORT_1 (1u << 1)
+#define PORT_2 (1u << 2)
+#define PORT_3 (1u << 3)
+#define PORT_4 (1u << 4)
+#define PORT_ALL (0xffffffffu)
+
+#define PARTN_MAP_ENTRY(partn, port_mask, nvtype) \
+{ (NVRAM_PARTITION_TYPE_##partn), (PORT_##port_mask), (EFX_NVRAM_##nvtype) }
+
/* Translate EFX NVRAM types to firmware partition types */
static ef10_parttbl_entry_t hunt_parttbl[] = {
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1, 2, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2, 3, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3, 4, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_LICENSE, 1, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 2, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 3, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 4, EFX_NVRAM_LICENSE}
+ /* partn ports nvtype */
+ PARTN_MAP_ENTRY(MC_FIRMWARE, ALL, MC_FIRMWARE),
+ PARTN_MAP_ENTRY(MC_FIRMWARE_BACKUP, ALL, MC_GOLDEN),
+ PARTN_MAP_ENTRY(EXPANSION_ROM, ALL, BOOTROM),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG_PORT0, 1, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG_PORT1, 2, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG_PORT2, 3, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG_PORT3, 4, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(DYNAMIC_CONFIG, ALL, DYNAMIC_CFG),
+ PARTN_MAP_ENTRY(FPGA, ALL, FPGA),
+ PARTN_MAP_ENTRY(FPGA_BACKUP, ALL, FPGA_BACKUP),
+ PARTN_MAP_ENTRY(LICENSE, ALL, LICENSE),
};
static ef10_parttbl_entry_t medford_parttbl[] = {
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 1, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 2, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 3, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE, 4, EFX_NVRAM_MC_FIRMWARE},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 1, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 2, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 3, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP, 4, EFX_NVRAM_MC_GOLDEN},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 1, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 2, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 3, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_ROM, 4, EFX_NVRAM_BOOTROM},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 1, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 2, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 3, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0, 4, EFX_NVRAM_BOOTROM_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 1, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 2, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 3, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG, 4, EFX_NVRAM_DYNAMIC_CFG},
- {NVRAM_PARTITION_TYPE_FPGA, 1, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 2, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 3, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA, 4, EFX_NVRAM_FPGA},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 1, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 2, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 3, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_FPGA_BACKUP, 4, EFX_NVRAM_FPGA_BACKUP},
- {NVRAM_PARTITION_TYPE_LICENSE, 1, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 2, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 3, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_LICENSE, 4, EFX_NVRAM_LICENSE},
- {NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 1, EFX_NVRAM_UEFIROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 2, EFX_NVRAM_UEFIROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 3, EFX_NVRAM_UEFIROM},
- {NVRAM_PARTITION_TYPE_EXPANSION_UEFI, 4, EFX_NVRAM_UEFIROM}
+ /* partn ports nvtype */
+ PARTN_MAP_ENTRY(MC_FIRMWARE, ALL, MC_FIRMWARE),
+ PARTN_MAP_ENTRY(MC_FIRMWARE_BACKUP, ALL, MC_GOLDEN),
+ PARTN_MAP_ENTRY(EXPANSION_ROM, ALL, BOOTROM),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG, ALL, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(DYNAMIC_CONFIG, ALL, DYNAMIC_CFG),
+ PARTN_MAP_ENTRY(FPGA, ALL, FPGA),
+ PARTN_MAP_ENTRY(FPGA_BACKUP, ALL, FPGA_BACKUP),
+ PARTN_MAP_ENTRY(LICENSE, ALL, LICENSE),
+ PARTN_MAP_ENTRY(EXPANSION_UEFI, ALL, UEFIROM),
+ PARTN_MAP_ENTRY(MUM_FIRMWARE, ALL, MUM_FIRMWARE),
+};
+
+static ef10_parttbl_entry_t medford2_parttbl[] = {
+ /* partn ports nvtype */
+ PARTN_MAP_ENTRY(MC_FIRMWARE, ALL, MC_FIRMWARE),
+ PARTN_MAP_ENTRY(MC_FIRMWARE_BACKUP, ALL, MC_GOLDEN),
+ PARTN_MAP_ENTRY(EXPANSION_ROM, ALL, BOOTROM),
+ PARTN_MAP_ENTRY(EXPROM_CONFIG, ALL, BOOTROM_CFG),
+ PARTN_MAP_ENTRY(DYNAMIC_CONFIG, ALL, DYNAMIC_CFG),
+ PARTN_MAP_ENTRY(FPGA, ALL, FPGA),
+ PARTN_MAP_ENTRY(FPGA_BACKUP, ALL, FPGA_BACKUP),
+ PARTN_MAP_ENTRY(LICENSE, ALL, LICENSE),
+ PARTN_MAP_ENTRY(EXPANSION_UEFI, ALL, UEFIROM),
+ PARTN_MAP_ENTRY(MUM_FIRMWARE, ALL, MUM_FIRMWARE),
+ PARTN_MAP_ENTRY(DYNCONFIG_DEFAULTS, ALL, DYNCONFIG_DEFAULTS),
+ PARTN_MAP_ENTRY(ROMCONFIG_DEFAULTS, ALL, ROMCONFIG_DEFAULTS),
+ PARTN_MAP_ENTRY(BUNDLE, ALL, BUNDLE),
+ PARTN_MAP_ENTRY(BUNDLE_METADATA, ALL, BUNDLE_METADATA),
};
static __checkReturn efx_rc_t
*parttbl_rowsp = EFX_ARRAY_SIZE(medford_parttbl);
break;
+ case EFX_FAMILY_MEDFORD2:
+ *parttblp = medford2_parttbl;
+ *parttbl_rowsp = EFX_ARRAY_SIZE(medford2_parttbl);
+ break;
+
default:
EFSYS_ASSERT(B_FALSE);
return (EINVAL);
size_t parttbl_rows = 0;
unsigned int i;
+ EFSYS_ASSERT3U(type, !=, EFX_NVRAM_INVALID);
EFSYS_ASSERT3U(type, <, EFX_NVRAM_NTYPES);
EFSYS_ASSERT(partnp != NULL);
for (i = 0; i < parttbl_rows; i++) {
ef10_parttbl_entry_t *entry = &parttbl[i];
- if (entry->nvtype == type &&
- entry->port == emip->emi_port) {
+ if ((entry->nvtype == type) &&
+ (entry->port_mask & (1u << emip->emi_port))) {
*partnp = entry->partn;
return (0);
}
for (i = 0; i < parttbl_rows; i++) {
ef10_parttbl_entry_t *entry = &parttbl[i];
- if (entry->partn == partn &&
- entry->port == emip->emi_port) {
+ if ((entry->partn == partn) &&
+ (entry->port_mask & (1u << emip->emi_port))) {
*typep = entry->nvtype;
return (0);
}
__in uint32_t partn,
__out size_t *chunk_sizep)
{
+ efx_nvram_info_t eni = { 0 };
efx_rc_t rc;
- if ((rc = ef10_nvram_partn_lock(enp, partn)) != 0)
+ if ((rc = ef10_nvram_partn_info(enp, partn, &eni)) != 0)
goto fail1;
+ if ((rc = ef10_nvram_partn_lock(enp, partn)) != 0)
+ goto fail2;
+
if (chunk_sizep != NULL)
- *chunk_sizep = EF10_NVRAM_CHUNK;
+ *chunk_sizep = eni.eni_write_size;
return (0);
+fail2:
+ EFSYS_PROBE(fail2);
fail1:
EFSYS_PROBE1(fail1, efx_rc_t, rc);
__checkReturn efx_rc_t
ef10_nvram_partn_rw_finish(
__in efx_nic_t *enp,
- __in uint32_t partn)
+ __in uint32_t partn,
+ __out_opt uint32_t *verify_resultp)
{
efx_rc_t rc;
- if ((rc = ef10_nvram_partn_unlock(enp, partn, NULL)) != 0)
+ if ((rc = ef10_nvram_partn_unlock(enp, partn, verify_resultp)) != 0)
goto fail1;
return (0);
#endif /* EFSYS_OPT_NVRAM */
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
+#endif /* EFX_OPTS_EF10() */