net/mlx5: rearrange creation of WQ and CQ object

[dpdk.git] / drivers / net / sfc / base / ef10_rx.c

diff --git a/drivers/net/sfc/base/ef10_rx.c b/drivers/net/sfc/base/ef10_rx.c
index b087a5d..bfa5533 100644 (file)
--- a/drivers/net/sfc/base/ef10_rx.c
+++ b/drivers/net/sfc/base/ef10_rx.c
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: BSD-3-Clause
  *
- * Copyright (c) 2012-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2012-2019 Solarflare Communications Inc.
  */
 
 #include "efx.h"
@@ -859,7 +859,7 @@ ef10_rx_qpush(
        efx_dword_t dword;
 
        /* Hardware has alignment restriction for WPTR */
-       wptr = P2ALIGN(added, EF10_RX_WPTR_ALIGN);
+       wptr = EFX_P2ALIGN(unsigned int, added, EF10_RX_WPTR_ALIGN);
        if (pushed == wptr)
                return;
 
@@ -1119,12 +1119,12 @@ ef10_rx_qcreate(
                        rc = ENOTSUP;
                        goto fail9;
                }
-               if (!IS_P2ALIGNED(es_max_dma_len,
+               if (!EFX_IS_P2ALIGNED(uint32_t, es_max_dma_len,
                            EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
                        rc = EINVAL;
                        goto fail10;
                }
-               if (!IS_P2ALIGNED(es_buf_stride,
+               if (!EFX_IS_P2ALIGNED(uint32_t, es_buf_stride,
                            EFX_RX_ES_SUPER_BUFFER_BUF_ALIGNMENT)) {
                        rc = EINVAL;
                        goto fail11;