* All rights reserved.
*/
+/*
+ * This is NOT the original source file. Do NOT edit it.
+ * To update the tlv layout, please edit the copy in
+ * the sfregistry repo and then, in that repo,
+ * "make tlv_headers" or "make export" to
+ * regenerate and export all types of headers.
+ */
+
/* These structures define the layouts for the TLV items stored in static and
* dynamic configuration partitions in NVRAM for EF10 (Huntington etc.).
*
#define TLV_FIRMWARE_VARIANT_PACKED_STREAM_HASH_MODE_1 \
MC_CMD_FW_PACKED_STREAM_HASH_MODE_1
#define TLV_FIRMWARE_VARIANT_RULES_ENGINE MC_CMD_FW_RULES_ENGINE
+#define TLV_FIRMWARE_VARIANT_DPDK MC_CMD_FW_DPDK
+#define TLV_FIRMWARE_VARIANT_L3XUDP MC_CMD_FW_L3XUDP
};
/* Voltage settings
uint32_t length;
uint32_t port_mode;
#define TLV_PORT_MODE_DEFAULT (0xffffffff) /* Default for given platform */
+
+/* Huntington port modes */
+#define TLV_PORT_MODE_10G (0)
+#define TLV_PORT_MODE_40G (1)
+#define TLV_PORT_MODE_10G_10G (2)
+#define TLV_PORT_MODE_40G_40G (3)
+#define TLV_PORT_MODE_10G_10G_10G_10G (4)
+#define TLV_PORT_MODE_40G_10G_10G (6)
+#define TLV_PORT_MODE_10G_10G_40G (7)
+
+/* Medford (and later) port modes */
#define TLV_PORT_MODE_1x1_NA (0) /* Single 10G/25G on mdi0 */
#define TLV_PORT_MODE_1x4_NA (1) /* Single 100G/40G on mdi0 */
#define TLV_PORT_MODE_NA_1x4 (22) /* Single 100G/40G on mdi1 */
#define TLV_PORT_MODE_NA_1x2 (11) /* Single 50G on mdi1 */
#define TLV_PORT_MODE_1x1_1x1 (2) /* Single 10G/25G on mdi0, single 10G/25G on mdi1 */
#define TLV_PORT_MODE_1x4_1x4 (3) /* Single 40G on mdi0, single 40G on mdi1 */
-#define TLV_PORT_MODE_2x1_2x1 (4) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 - WARNING: bug3720: On Newport only, this is actually Quad 10G on mdi0 */
-#define TLV_PORT_MODE_4x1_NA (5) /* Quad 10G/25G on mdi0 */
+#define TLV_PORT_MODE_2x1_2x1 (5) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1 */
+#define TLV_PORT_MODE_4x1_NA (4) /* Quad 10G/25G on mdi0 */
#define TLV_PORT_MODE_NA_4x1 (8) /* Quad 10G/25G on mdi1 */
#define TLV_PORT_MODE_1x4_2x1 (6) /* Single 40G on mdi0, dual 10G/25G on mdi1 */
#define TLV_PORT_MODE_2x1_1x4 (7) /* Dual 10G/25G on mdi0, single 40G on mdi1 */
#define TLV_PORT_MODE_1x2_1x4 (16) /* Single 50G on mdi0, single 40G on mdi1 */
#define TLV_PORT_MODE_1x2_2x1 (17) /* Single 50G on mdi0, dual 10G/25G on mdi1 */
#define TLV_PORT_MODE_2x1_1x2 (18) /* Dual 10G/25G on mdi0, single 50G on mdi1 */
-/* Below modes are eftest only, to allow snapper explicit selection between multi-channel and LLPCS. In production, this selection is automatic and outside world should not care about LLPCS */
+
+/* Snapper-only Medford2 port modes.
+ * These modes are eftest only, to allow snapper explicit
+ * selection between multi-channel and LLPCS. In production,
+ * this selection is automatic and outside world should not
+ * care about LLPCS.
+ */
#define TLV_PORT_MODE_2x1_2x1_LL (19) /* Dual 10G/25G on mdi0, dual 10G/25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_4x1_NA_LL (20) /* Quad 10G/25G on mdi0, low-latency PCS */
#define TLV_PORT_MODE_NA_4x1_LL (21) /* Quad 10G/25G on mdi1, low-latency PCS */
#define TLV_PORT_MODE_BUG63720_DO_NOT_USE (9) /* bug63720: Do not use */
#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
-/* Deprecated aliases */
-#define TLV_PORT_MODE_10G TLV_PORT_MODE_1x1_NA
-#define TLV_PORT_MODE_40G TLV_PORT_MODE_1x4_NA
-#define TLV_PORT_MODE_10G_10G TLV_PORT_MODE_1x1_1x1
-#define TLV_PORT_MODE_40G_40G TLV_PORT_MODE_1x4_1x4
-#define TLV_PORT_MODE_10G_10G_10G_10G TLV_PORT_MODE_2x1_2x1
-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 TLV_PORT_MODE_2x1_2x1 /* bug63720: Do not use */
-#define TLV_PORT_MODE_10G_10G_10G_10G_Q TLV_PORT_MODE_4x1_NA
-#define TLV_PORT_MODE_40G_10G_10G TLV_PORT_MODE_1x4_2x1
-#define TLV_PORT_MODE_10G_10G_40G TLV_PORT_MODE_2x1_1x4
-#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 TLV_PORT_MODE_NA_4x1
-#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 TLV_PORT_MODE_BUG63720_DO_NOT_USE /* bug63720: Do not use */
-#define TLV_PORT_MODE_25G TLV_PORT_MODE_1x1_NA /* Single 25G on mdi0 */
-#define TLV_PORT_MODE_100G_Q1 TLV_PORT_MODE_1x4_NA /* Single 100G on mdi0 */
-#define TLV_PORT_MODE_100G_Q2 TLV_PORT_MODE_NA_1x4 /* Single 100G on mdi1 */
-#define TLV_PORT_MODE_50G_Q1 TLV_PORT_MODE_1x2_NA /* Single 50G on mdi0 */
-#define TLV_PORT_MODE_50G_Q2 TLV_PORT_MODE_NA_1x2 /* Single 50G on mdi1 */
-#define TLV_PORT_MODE_25G_25G TLV_PORT_MODE_1x1_1x1 /* Single 25G on mdi0, single 25G on mdi1 */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2 TLV_PORT_MODE_2x1_2x1 /* Dual 25G on mdi0, dual 25G on mdi1 */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1 TLV_PORT_MODE_4x1_NA /* Quad 25G on mdi0 */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q2 TLV_PORT_MODE_NA_4x1 /* Quad 25G on mdi1 */
-#define TLV_PORT_MODE_40G_25G_25G TLV_PORT_MODE_1x4_2x1 /* Single 40G on mdi0, dual 25G on mdi1 */
-#define TLV_PORT_MODE_25G_25G_40G TLV_PORT_MODE_2x1_1x4 /* Dual 25G on mdi0, single 40G on mdi1 */
-#define TLV_PORT_MODE_50G_50G_Q1_Q2 TLV_PORT_MODE_1x2_1x2 /* Single 50G on mdi0, single 50G on mdi1 */
-#define TLV_PORT_MODE_50G_50G_Q1 TLV_PORT_MODE_2x2_NA /* Dual 50G on mdi0 */
-#define TLV_PORT_MODE_50G_50G_Q2 TLV_PORT_MODE_NA_2x2 /* Dual 50G on mdi1 */
-#define TLV_PORT_MODE_40G_50G TLV_PORT_MODE_1x4_1x2 /* Single 40G on mdi0, single 50G on mdi1 */
-#define TLV_PORT_MODE_50G_40G TLV_PORT_MODE_1x2_1x4 /* Single 50G on mdi0, single 40G on mdi1 */
-#define TLV_PORT_MODE_50G_25G_25G TLV_PORT_MODE_1x2_2x1 /* Single 50G on mdi0, dual 25G on mdi1 */
-#define TLV_PORT_MODE_25G_25G_50G TLV_PORT_MODE_2x1_1x2 /* Dual 25G on mdi0, single 50G on mdi1 */
-/* eftest only, see comments for _LL modes above */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_Q2_LL TLV_PORT_MODE_2x1_2x1_LL /* Dual 25G on mdi0, dual 25G on mdi1, low-latency PCS */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q1_LL TLV_PORT_MODE_4x1_NA_LL /* Quad 25G on mdi0, low-latency PCS */
-#define TLV_PORT_MODE_25G_25G_25G_25G_Q2_LL TLV_PORT_MODE_NA_4x1_LL /* Quad 25G on mdi1, low-latency PCS */
-#define TLV_PORT_MODE_25G_LL TLV_PORT_MODE_1x1_NA_LL /* Single 10G/25G on mdi0, low-latency PCS */
-#define TLV_PORT_MODE_25G_25G_LL TLV_PORT_MODE_1x1_1x1_LL /* Single 10G/25G on mdi0, single 10G/25G on mdi1, low-latency PCS */
+/* Deprecated Medford aliases - DO NOT USE IN NEW CODE */
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q (5)
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1 (4)
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q2 (8)
+#define TLV_PORT_MODE_10G_10G_10G_10G_Q1_Q2 (9)
+
+#define TLV_PORT_MODE_MAX TLV_PORT_MODE_1x1_1x1_LL
};
/* Type of the v-switch created implicitly by the firmware */
#define TLV_FASTPD_MODE_FAST_SUPPORTED 2 /* Supported packet types to the FastPD; everything else to the SoftPD */
};
+/* L3xUDP datapath firmware UDP port configuration
+ *
+ * Sets the list of UDP ports on which the encapsulation will be handled.
+ * The number of ports in the list is implied by the length of the TLV item.
+ */
+#define TLV_TAG_L3XUDP_PORTS (0x102a0000)
+struct tlv_l3xudp_ports {
+ uint32_t tag;
+ uint32_t length;
+ uint16_t ports[];
+#define TLV_TAG_L3XUDP_PORTS_MAX_NUM_PORTS 16
+};
+
#endif /* CI_MGMT_TLV_LAYOUT_H */
git.droids-corp.org / dpdk.git / blobdiff