-/*
- * Copyright (c) 2012-2016 Solarflare Communications Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+/* SPDX-License-Identifier: BSD-3-Clause
*
- * The views and conclusions contained in the software and documentation are
- * those of the authors and should not be interpreted as representing official
- * policies, either expressed or implied, of the FreeBSD Project.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2012-2019 Solarflare Communications Inc.
*/
#include "efx.h"
#include "efx_impl.h"
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
+#if EFX_OPTS_EF10()
#if EFSYS_OPT_QSTATS
#define EFX_TX_QSTAT_INCR(_etp, _stat) \
__in efsys_mem_t *esmp)
{
efx_mcdi_req_t req;
- uint8_t payload[MAX(MC_CMD_INIT_TXQ_IN_LEN(EFX_TXQ_MAX_BUFS),
- MC_CMD_INIT_TXQ_OUT_LEN)];
+ EFX_MCDI_DECLARE_BUF(payload,
+ MC_CMD_INIT_TXQ_IN_LEN(EF10_TXQ_MAXNBUFS),
+ MC_CMD_INIT_TXQ_OUT_LEN);
efx_qword_t *dma_addr;
uint64_t addr;
int npages;
int i;
efx_rc_t rc;
- EFSYS_ASSERT(EFX_TXQ_MAX_BUFS >=
- EFX_TXQ_NBUFS(enp->en_nic_cfg.enc_txq_max_ndescs));
+ EFSYS_ASSERT(EF10_TXQ_MAXNBUFS >=
+ efx_txq_nbufs(enp, enp->en_nic_cfg.enc_txq_max_ndescs));
- npages = EFX_TXQ_NBUFS(ndescs);
- if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
+ if ((esmp == NULL) ||
+ (EFSYS_MEM_SIZE(esmp) < efx_txq_size(enp, ndescs))) {
rc = EINVAL;
goto fail1;
}
- (void) memset(payload, 0, sizeof (payload));
+ npages = efx_txq_nbufs(enp, ndescs);
+ if (MC_CMD_INIT_TXQ_IN_LEN(npages) > sizeof (payload)) {
+ rc = EINVAL;
+ goto fail2;
+ }
+
req.emr_cmd = MC_CMD_INIT_TXQ;
req.emr_in_buf = payload;
req.emr_in_length = MC_CMD_INIT_TXQ_IN_LEN(npages);
INIT_TXQ_IN_FLAG_TIMESTAMP, 0);
MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_OWNER_ID, 0);
- MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, EVB_PORT_ID_ASSIGNED);
+ MCDI_IN_SET_DWORD(req, INIT_TXQ_IN_PORT_ID, enp->en_vport_id);
dma_addr = MCDI_IN2(req, efx_qword_t, INIT_TXQ_IN_DMA_ADDR);
addr = EFSYS_MEM_ADDR(esmp);
if (req.emr_rc != 0) {
rc = req.emr_rc;
- goto fail2;
+ goto fail3;
}
return (0);
+fail3:
+ EFSYS_PROBE(fail3);
fail2:
EFSYS_PROBE(fail2);
fail1:
__in uint32_t instance)
{
efx_mcdi_req_t req;
- uint8_t payload[MAX(MC_CMD_FINI_TXQ_IN_LEN,
- MC_CMD_FINI_TXQ_OUT_LEN)];
+ EFX_MCDI_DECLARE_BUF(payload, MC_CMD_FINI_TXQ_IN_LEN,
+ MC_CMD_FINI_TXQ_OUT_LEN);
efx_rc_t rc;
- (void) memset(payload, 0, sizeof (payload));
req.emr_cmd = MC_CMD_FINI_TXQ;
req.emr_in_buf = payload;
req.emr_in_length = MC_CMD_FINI_TXQ_IN_LEN;
{
efx_nic_cfg_t *encp = &enp->en_nic_cfg;
uint16_t inner_csum;
- efx_qword_t desc;
+ efx_desc_t desc;
efx_rc_t rc;
_NOTE(ARGUNUSED(id))
* a no-op TX option descriptor. See bug29981 for details.
*/
*addedp = 1;
- EFX_POPULATE_QWORD_6(desc,
- ESF_DZ_TX_DESC_IS_OPT, 1,
- ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
- ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
- (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
- ESF_DZ_TX_OPTION_IP_CSUM,
- (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
- ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
- (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
- ESF_DZ_TX_OPTION_INNER_IP_CSUM,
- (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
+ ef10_tx_qdesc_checksum_create(etp, flags, &desc);
- EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc);
+ EFSYS_MEM_WRITEQ(etp->et_esmp, 0, &desc.ed_eq);
ef10_tx_qpush(etp, *addedp, 0);
return (0);
fail3:
EFSYS_PROBE(fail3);
- ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
+ (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
fail2:
EFSYS_PROBE(fail2);
etp->et_pio_size = 0;
if (etp->et_pio_size != 0) {
/* Unlink the piobuf from this TXQ */
- ef10_nic_pio_unlink(enp, etp->et_index);
+ if (ef10_nic_pio_unlink(enp, etp->et_index) != 0)
+ return;
/* Free the sub-allocated PIO block */
- ef10_nic_pio_free(enp, etp->et_pio_bufnum, etp->et_pio_blknum);
+ (void) ef10_nic_pio_free(enp, etp->et_pio_bufnum,
+ etp->et_pio_blknum);
etp->et_pio_size = 0;
etp->et_pio_write_offset = 0;
}
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
wptr, id);
EFSYS_PIO_WRITE_BARRIER();
- EFX_BAR_TBL_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
- etp->et_index, &oword);
+ EFX_BAR_VI_DOORBELL_WRITEO(enp, ER_DZ_TX_DESC_UPD_REG,
+ etp->et_index, &oword);
} else {
efx_dword_t dword;
EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
wptr, id);
EFSYS_PIO_WRITE_BARRIER();
- EFX_BAR_TBL_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
- etp->et_index, &dword, B_FALSE);
+ EFX_BAR_VI_WRITED2(enp, ER_DZ_TX_DESC_UPD_REG,
+ etp->et_index, &dword, B_FALSE);
}
}
{
unsigned int added = *addedp;
unsigned int i;
- efx_rc_t rc;
- if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
- rc = ENOSPC;
- goto fail1;
- }
+ if (added - completed + ndescs > EFX_TXQ_LIMIT(etp->et_mask + 1))
+ return (ENOSPC);
for (i = 0; i < ndescs; i++) {
efx_desc_t *edp = &ed[i];
*addedp = added;
return (0);
-
-fail1:
- EFSYS_PROBE1(fail1, efx_rc_t, rc);
-
- return (rc);
}
void
__in boolean_t eop,
__out efx_desc_t *edp)
{
+ _NOTE(ARGUNUSED(etp))
+
/* No limitations on boundary crossing */
EFSYS_ASSERT(size <= etp->et_enp->en_nic_cfg.enc_tx_dma_desc_size_max);
__in uint8_t tcp_flags,
__out efx_desc_t *edp)
{
+ _NOTE(ARGUNUSED(etp))
+
EFSYS_PROBE4(tx_desc_tso_create, unsigned int, etp->et_index,
uint16_t, ipv4_id, uint32_t, tcp_seq,
uint8_t, tcp_flags);
ef10_tx_qdesc_tso2_create(
__in efx_txq_t *etp,
__in uint16_t ipv4_id,
+ __in uint16_t outer_ipv4_id,
__in uint32_t tcp_seq,
__in uint16_t tcp_mss,
__out_ecount(count) efx_desc_t *edp,
__in int count)
{
+ _NOTE(ARGUNUSED(etp, count))
+
EFSYS_PROBE4(tx_desc_tso2_create, unsigned int, etp->et_index,
uint16_t, ipv4_id, uint32_t, tcp_seq,
uint16_t, tcp_mss);
ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A,
ESF_DZ_TX_TSO_IP_ID, ipv4_id,
ESF_DZ_TX_TSO_TCP_SEQNO, tcp_seq);
- EFX_POPULATE_QWORD_4(edp[1].ed_eq,
+ EFX_POPULATE_QWORD_5(edp[1].ed_eq,
ESF_DZ_TX_DESC_IS_OPT, 1,
ESF_DZ_TX_OPTION_TYPE,
ESE_DZ_TX_OPTION_DESC_TSO,
ESF_DZ_TX_TSO_OPTION_TYPE,
ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B,
- ESF_DZ_TX_TSO_TCP_MSS, tcp_mss);
+ ESF_DZ_TX_TSO_TCP_MSS, tcp_mss,
+ ESF_DZ_TX_TSO_OUTER_IPID, outer_ipv4_id);
}
void
__in uint16_t tci,
__out efx_desc_t *edp)
{
+ _NOTE(ARGUNUSED(etp))
+
EFSYS_PROBE2(tx_desc_vlantci_create, unsigned int, etp->et_index,
uint16_t, tci);
ESF_DZ_TX_VLAN_TAG1, tci);
}
+ void
+ef10_tx_qdesc_checksum_create(
+ __in efx_txq_t *etp,
+ __in uint16_t flags,
+ __out efx_desc_t *edp)
+{
+ _NOTE(ARGUNUSED(etp));
+
+ EFSYS_PROBE2(tx_desc_checksum_create, unsigned int, etp->et_index,
+ uint32_t, flags);
+
+ EFX_POPULATE_QWORD_6(edp->ed_eq,
+ ESF_DZ_TX_DESC_IS_OPT, 1,
+ ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_CRC_CSUM,
+ ESF_DZ_TX_OPTION_UDP_TCP_CSUM,
+ (flags & EFX_TXQ_CKSUM_TCPUDP) ? 1 : 0,
+ ESF_DZ_TX_OPTION_IP_CSUM,
+ (flags & EFX_TXQ_CKSUM_IPV4) ? 1 : 0,
+ ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM,
+ (flags & EFX_TXQ_CKSUM_INNER_TCPUDP) ? 1 : 0,
+ ESF_DZ_TX_OPTION_INNER_IP_CSUM,
+ (flags & EFX_TXQ_CKSUM_INNER_IPV4) ? 1 : 0);
+}
+
__checkReturn efx_rc_t
ef10_tx_qpace(
#endif /* EFSYS_OPT_QSTATS */
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
+#endif /* EFX_OPTS_EF10() */
git.droids-corp.org / dpdk.git / blobdiff