efx_intr_init(
__in efx_nic_t *enp,
__in efx_intr_type_t type,
- __in efsys_mem_t *esmp);
+ __in_opt efsys_mem_t *esmp);
extern void
efx_intr_enable(
__in efx_nic_t *enp,
__out efx_phy_media_type_t *typep);
+/*
+ * 2-wire device address of the base information in accordance with SFF-8472
+ * Diagnostic Monitoring Interface for Optical Transceivers section
+ * 4 Memory Organization.
+ */
+#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
+
+/*
+ * 2-wire device address of the digital diagnostics monitoring interface
+ * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
+ * Transceivers section 4 Memory Organization.
+ */
+#define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
+
+/*
+ * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
+ * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
+ * Operation.
+ */
+#define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
+
+/*
+ * Maximum accessible data offset for PHY module information.
+ */
+#define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
+
+
extern __checkReturn efx_rc_t
efx_phy_module_get_info(
__in efx_nic_t *enp,
__in uint8_t dev_addr,
- __in uint8_t offset,
- __in uint8_t len,
+ __in size_t offset,
+ __in size_t len,
__out_bcount(len) uint8_t *data);
#if EFSYS_OPT_PHY_STATS
#define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
#define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
#define EFX_FEATURE_PACKED_STREAM 0x00004000
+#define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
typedef enum efx_tunnel_protocol_e {
EFX_TUNNEL_PROTOCOL_NONE = 0,
uint32_t enc_evq_limit;
uint32_t enc_txq_limit;
uint32_t enc_rxq_limit;
+ uint32_t enc_evq_max_nevs;
+ uint32_t enc_evq_min_nevs;
+ uint32_t enc_rxq_max_ndescs;
+ uint32_t enc_rxq_min_ndescs;
uint32_t enc_txq_max_ndescs;
+ uint32_t enc_txq_min_ndescs;
uint32_t enc_buftbl_limit;
uint32_t enc_piobuf_limit;
uint32_t enc_piobuf_size;
uint32_t enc_rx_prefix_size;
uint32_t enc_rx_buf_align_start;
uint32_t enc_rx_buf_align_end;
+#if EFSYS_OPT_RX_SCALE
uint32_t enc_rx_scale_max_exclusive_contexts;
/*
* Mask of supported hash algorithms.
*/
boolean_t enc_rx_scale_l4_hash_supported;
boolean_t enc_rx_scale_additional_modes_supported;
+#endif /* EFSYS_OPT_RX_SCALE */
#if EFSYS_OPT_LOOPBACK
efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
#endif /* EFSYS_OPT_LOOPBACK */
efx_ev_fini(
__in efx_nic_t *enp);
+/*
+ * These symbols are deprecated and will be removed.
+ * Use the fields from efx_nic_cfg_t instead.
+ */
#define EFX_EVQ_MAXNEVS 32768
#define EFX_EVQ_MINNEVS 512
* - a combination of legacy flags
* - a combination of EFX_RX_HASH() flags
*/
-typedef unsigned int efx_rx_hash_type_t;
+typedef uint32_t efx_rx_hash_type_t;
typedef enum efx_rx_hash_support_e {
EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
efx_rx_scale_hash_flags_get(
__in efx_nic_t *enp,
__in efx_rx_hash_alg_t hash_alg,
- __inout_ecount(EFX_RX_HASH_NFLAGS) unsigned int *flagsp,
+ __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
+ __in unsigned int max_nflags,
__out unsigned int *nflagsp);
extern __checkReturn efx_rc_t
__in uint8_t *buffer,
__out uint16_t *pkt_lengthp);
-#define EFX_RXQ_MAXNDESCS 4096
-#define EFX_RXQ_MINNDESCS 512
+/*
+ * These symbols are deprecated and will be removed.
+ * Use the fields from efx_nic_cfg_t instead.
+ */
+#define EFX_RXQ_MAXNDESCS 4096
+#define EFX_RXQ_MINNDESCS 512
#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
#define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
-#define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
typedef enum efx_rxq_type_e {
EFX_RXQ_TYPE_DEFAULT,
efx_tx_fini(
__in efx_nic_t *enp);
+/*
+ * This symbol is deprecated and will be removed.
+ * Use the field from efx_nic_cfg_t instead.
+ */
#define EFX_TXQ_MINNDESCS 512
#define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
efx_filter_flags_t efs_flags;
uint16_t efs_dmaq_id;
uint32_t efs_rss_context;
+ uint32_t efs_mark;
+ /* Fields below here are hashed for software filter lookup */
uint16_t efs_outer_vid;
uint16_t efs_inner_vid;
uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
efx_oword_t efs_loc_host;
uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
- uint32_t efs_mark;
} efx_filter_spec_t;
__in efx_filter_inner_frame_match_t inner_frame_match);
extern __checkReturn efx_rc_t
-efx_filter_spec_set_vxlan_full(
+efx_filter_spec_set_vxlan(
+ __inout efx_filter_spec_t *spec,
+ __in const uint8_t *vni,
+ __in const uint8_t *inner_addr,
+ __in const uint8_t *outer_addr);
+
+extern __checkReturn efx_rc_t
+efx_filter_spec_set_geneve(
+ __inout efx_filter_spec_t *spec,
+ __in const uint8_t *vni,
+ __in const uint8_t *inner_addr,
+ __in const uint8_t *outer_addr);
+
+extern __checkReturn efx_rc_t
+efx_filter_spec_set_nvgre(
__inout efx_filter_spec_t *spec,
- __in const uint8_t *vxlan_id,
+ __in const uint8_t *vsid,
__in const uint8_t *inner_addr,
__in const uint8_t *outer_addr);
#endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
+typedef enum efx_phy_fec_type_e {
+ EFX_PHY_FEC_NONE = 0,
+ EFX_PHY_FEC_BASER,
+ EFX_PHY_FEC_RS
+} efx_phy_fec_type_t;
+
+extern __checkReturn efx_rc_t
+efx_phy_fec_type_get(
+ __in efx_nic_t *enp,
+ __out efx_phy_fec_type_t *typep);
+
+typedef struct efx_phy_link_state_s {
+ uint32_t epls_adv_cap_mask;
+ uint32_t epls_lp_cap_mask;
+ uint32_t epls_ld_cap_mask;
+ unsigned int epls_fcntl;
+ efx_phy_fec_type_t epls_fec;
+ efx_link_mode_t epls_link_mode;
+} efx_phy_link_state_t;
+
+extern __checkReturn efx_rc_t
+efx_phy_link_state_get(
+ __in efx_nic_t *enp,
+ __out efx_phy_link_state_t *eplsp);
+
+
#ifdef __cplusplus
}
#endif
git.droids-corp.org / dpdk.git / blobdiff