#define EFX_MAC_STATS_SIZE 0x400
+extern __checkReturn efx_rc_t
+efx_mac_stats_clear(
+ __in efx_nic_t *enp);
+
/*
* Upload mac statistics supported by the hardware into the given buffer.
*
uint32_t enc_rx_batch_max;
/* Number of rx descriptors the hardware requires for a push. */
uint32_t enc_rx_push_align;
+ /* Maximum amount of data in DMA descriptor */
+ uint32_t enc_tx_dma_desc_size_max;
+ /*
+ * Boundary which DMA descriptor data must not cross or 0 if no
+ * limitation.
+ */
+ uint32_t enc_tx_dma_desc_boundary;
/*
* Maximum number of bytes into the packet the TCP header can start for
* the hardware to apply TSO packet edits.
EFX_RX_HASHALG_TOEPLITZ
} efx_rx_hash_alg_t;
-typedef enum efx_rx_hash_type_e {
- EFX_RX_HASH_IPV4 = 0,
- EFX_RX_HASH_TCPIPV4,
- EFX_RX_HASH_IPV6,
- EFX_RX_HASH_TCPIPV6,
-} efx_rx_hash_type_t;
+#define EFX_RX_HASH_IPV4 (1U << 0)
+#define EFX_RX_HASH_TCPIPV4 (1U << 1)
+#define EFX_RX_HASH_IPV6 (1U << 2)
+#define EFX_RX_HASH_TCPIPV6 (1U << 3)
+
+typedef unsigned int efx_rx_hash_type_t;
typedef enum efx_rx_hash_support_e {
EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */