/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright (c) 2007-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2007-2019 Solarflare Communications Inc.
*/
#include "efx.h"
siena_phy_reconfigure, /* epo_reconfigure */
siena_phy_verify, /* epo_verify */
siena_phy_oui_get, /* epo_oui_get */
- NULL, /* epo_fec_type_get */
+ NULL, /* epo_link_state_get */
#if EFSYS_OPT_PHY_STATS
siena_phy_stats_update, /* epo_stats_update */
#endif /* EFSYS_OPT_PHY_STATS */
};
#endif /* EFSYS_OPT_SIENA */
-#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
+#if EFX_OPTS_EF10()
static const efx_phy_ops_t __efx_phy_ef10_ops = {
ef10_phy_power, /* epo_power */
NULL, /* epo_reset */
ef10_phy_reconfigure, /* epo_reconfigure */
ef10_phy_verify, /* epo_verify */
ef10_phy_oui_get, /* epo_oui_get */
- ef10_phy_fec_type_get, /* epo_fec_type_get */
+ ef10_phy_link_state_get, /* epo_link_state_get */
#if EFSYS_OPT_PHY_STATS
ef10_phy_stats_update, /* epo_stats_update */
#endif /* EFSYS_OPT_PHY_STATS */
ef10_bist_stop, /* epo_bist_stop */
#endif /* EFSYS_OPT_BIST */
};
-#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
+#endif /* EFX_OPTS_EF10() */
__checkReturn efx_rc_t
efx_phy_probe(
}
}
-#define EFX_PHY_CAP_FEC_REQ_MASK \
- (1U << EFX_PHY_CAP_BASER_FEC_REQUESTED) | \
- (1U << EFX_PHY_CAP_RS_FEC_REQUESTED) | \
- (1U << EFX_PHY_CAP_25G_BASER_FEC_REQUESTED)
-
__checkReturn efx_rc_t
efx_phy_adv_cap_set(
__in efx_nic_t *enp,
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PORT);
- /* Ignore don't care bits of FEC (FEC EFX_PHY_CAP_*_REQUESTED) */
- if ((mask & ~(epp->ep_phy_cap_mask | EFX_PHY_CAP_FEC_REQ_MASK)) != 0) {
+ if ((mask & ~epp->ep_phy_cap_mask) != 0) {
rc = ENOTSUP;
goto fail1;
}
efx_phy_module_get_info(
__in efx_nic_t *enp,
__in uint8_t dev_addr,
- __in uint8_t offset,
- __in uint8_t len,
+ __in size_t offset,
+ __in size_t len,
__out_bcount(len) uint8_t *data)
{
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
EFSYS_ASSERT(data != NULL);
- if ((uint32_t)offset + len > 0xff) {
+ if ((offset > EFX_PHY_MEDIA_INFO_MAX_OFFSET) ||
+ ((offset + len) > EFX_PHY_MEDIA_INFO_MAX_OFFSET)) {
rc = EINVAL;
goto fail1;
}
efx_phy_fec_type_get(
__in efx_nic_t *enp,
__out efx_phy_fec_type_t *typep)
+{
+ efx_rc_t rc;
+ efx_phy_link_state_t epls;
+
+ if ((rc = efx_phy_link_state_get(enp, &epls)) != 0)
+ goto fail1;
+
+ *typep = epls.epls_fec;
+
+ return (0);
+
+fail1:
+ EFSYS_PROBE1(fail1, efx_rc_t, rc);
+
+ return (rc);
+}
+
+ __checkReturn efx_rc_t
+efx_phy_link_state_get(
+ __in efx_nic_t *enp,
+ __out efx_phy_link_state_t *eplsp)
{
efx_port_t *epp = &(enp->en_port);
const efx_phy_ops_t *epop = epp->ep_epop;
efx_rc_t rc;
EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
+ EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
- if (epop->epo_fec_type_get == NULL) {
+ if (epop->epo_link_state_get == NULL) {
rc = ENOTSUP;
goto fail1;
}
- if ((rc = epop->epo_fec_type_get(enp, typep)) != 0)
+ if ((rc = epop->epo_link_state_get(enp, eplsp)) != 0)
goto fail2;
return (0);