* All rights reserved.
*/
-/*! \cidoxg_firmware_mc_cmd */
+/*
+ * This file is automatically generated. DO NOT EDIT IT.
+ * To make changes, edit the .yml files in sfregistry under doc/mcdi/ and
+ * rebuild this file with "make -C doc mcdiheaders".
+ */
#ifndef _SIENA_MC_DRIVER_PCOL_AOE_H
#define _SIENA_MC_DRIVER_PCOL_AOE_H
/* MC_CMD_FC_IN_WRITE32 msgrequest */
#define MC_CMD_FC_IN_WRITE32_LENMIN 16
#define MC_CMD_FC_IN_WRITE32_LENMAX 252
+#define MC_CMD_FC_IN_WRITE32_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_WRITE32_LEN(num) (12+4*(num))
+#define MC_CMD_FC_IN_WRITE32_BUFFER_NUM(len) (((len)-12)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_WRITE32_ADDR_HI_OFST 4
#define MC_CMD_FC_IN_WRITE32_BUFFER_LEN 4
#define MC_CMD_FC_IN_WRITE32_BUFFER_MINNUM 1
#define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM 60
+#define MC_CMD_FC_IN_WRITE32_BUFFER_MAXNUM_MCDI2 252
/* MC_CMD_FC_IN_TRC_READ msgrequest */
#define MC_CMD_FC_IN_TRC_READ_LEN 12
/* MC_CMD_FC_IN_IO_REL_WRITE32 msgrequest */
#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMIN 20
#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX 252
+#define MC_CMD_FC_IN_IO_REL_WRITE32_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_IO_REL_WRITE32_LEN(num) (16+4*(num))
+#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_NUM(len) (((len)-16)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
/* MC_CMD_FC_IN_IO_REL_HEADER_OFST 4 */
#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_LEN 4
#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MINNUM 1
#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM 59
+#define MC_CMD_FC_IN_IO_REL_WRITE32_BUFFER_MAXNUM_MCDI2 251
/* MC_CMD_FC_IN_UHLINK msgrequest */
#define MC_CMD_FC_IN_UHLINK_LEN 8
/* MC_CMD_FC_IN_SPI_WRITE msgrequest */
#define MC_CMD_FC_IN_SPI_WRITE_LENMIN 16
#define MC_CMD_FC_IN_SPI_WRITE_LENMAX 252
+#define MC_CMD_FC_IN_SPI_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_FC_IN_SPI_WRITE_LEN(num) (12+4*(num))
+#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_NUM(len) (((len)-12)/4)
/* MC_CMD_FC_IN_CMD_OFST 0 */
/* MC_CMD_FC_IN_CMD_LEN 4 */
#define MC_CMD_FC_IN_SPI_WRITE_OP_OFST 4
#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_LEN 4
#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MINNUM 1
#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM 60
+#define MC_CMD_FC_IN_SPI_WRITE_BUFFER_MAXNUM_MCDI2 252
/* MC_CMD_FC_IN_SPI_ERASE msgrequest */
#define MC_CMD_FC_IN_SPI_ERASE_LEN 16
/* MC_CMD_FC_OUT_READ32 msgresponse */
#define MC_CMD_FC_OUT_READ32_LENMIN 4
#define MC_CMD_FC_OUT_READ32_LENMAX 252
+#define MC_CMD_FC_OUT_READ32_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_READ32_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_READ32_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_READ32_BUFFER_OFST 0
#define MC_CMD_FC_OUT_READ32_BUFFER_LEN 4
#define MC_CMD_FC_OUT_READ32_BUFFER_MINNUM 1
#define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM 63
+#define MC_CMD_FC_OUT_READ32_BUFFER_MAXNUM_MCDI2 255
/* MC_CMD_FC_OUT_WRITE32 msgresponse */
#define MC_CMD_FC_OUT_WRITE32_LEN 0
/* MC_CMD_FC_OUT_IO_REL_READ32 msgresponse */
#define MC_CMD_FC_OUT_IO_REL_READ32_LENMIN 4
#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX 252
+#define MC_CMD_FC_OUT_IO_REL_READ32_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_IO_REL_READ32_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_OFST 0
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_LEN 4
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MINNUM 1
#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM 63
+#define MC_CMD_FC_OUT_IO_REL_READ32_BUFFER_MAXNUM_MCDI2 255
/* MC_CMD_FC_OUT_IO_REL_WRITE32 msgresponse */
#define MC_CMD_FC_OUT_IO_REL_WRITE32_LEN 0
/* MC_CMD_FC_OUT_DMA_READ msgresponse */
#define MC_CMD_FC_OUT_DMA_READ_LENMIN 1
#define MC_CMD_FC_OUT_DMA_READ_LENMAX 252
+#define MC_CMD_FC_OUT_DMA_READ_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_DMA_READ_LEN(num) (0+1*(num))
+#define MC_CMD_FC_OUT_DMA_READ_DATA_NUM(len) (((len)-0)/1)
/* The data read */
#define MC_CMD_FC_OUT_DMA_READ_DATA_OFST 0
#define MC_CMD_FC_OUT_DMA_READ_DATA_LEN 1
#define MC_CMD_FC_OUT_DMA_READ_DATA_MINNUM 1
#define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM 252
+#define MC_CMD_FC_OUT_DMA_READ_DATA_MAXNUM_MCDI2 1020
/* MC_CMD_FC_OUT_TIMED_READ_SET msgresponse */
#define MC_CMD_FC_OUT_TIMED_READ_SET_LEN 4
/* MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT msgresponse */
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMIN 8
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX 248
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LENMAX_MCDI2 1016
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_LEN(num) (0+8*(num))
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_NUM(len) (((len)-0)/8)
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_OFST 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_SECONDS_LEN 4
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_NANOSECONDS_OFST 4
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_HI_OFST 4
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MINNUM 0
#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM 31
+#define MC_CMD_FC_OUT_TIMESTAMP_READ_SNAPSHOT_TIMESTAMP_MAXNUM_MCDI2 127
/* MC_CMD_FC_OUT_SPI_READ msgresponse */
#define MC_CMD_FC_OUT_SPI_READ_LENMIN 4
#define MC_CMD_FC_OUT_SPI_READ_LENMAX 252
+#define MC_CMD_FC_OUT_SPI_READ_LENMAX_MCDI2 1020
#define MC_CMD_FC_OUT_SPI_READ_LEN(num) (0+4*(num))
+#define MC_CMD_FC_OUT_SPI_READ_BUFFER_NUM(len) (((len)-0)/4)
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_OFST 0
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_LEN 4
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MINNUM 1
#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM 63
+#define MC_CMD_FC_OUT_SPI_READ_BUFFER_MAXNUM_MCDI2 255
/* MC_CMD_FC_OUT_SPI_WRITE msgresponse */
#define MC_CMD_FC_OUT_SPI_WRITE_LEN 0
#define MC_CMD_AOE_OP_GET_ASIC_PORTS 0x19
/* enum: Get FC assert information and register dump */
#define MC_CMD_AOE_OP_GET_FC_ASSERT_INFO 0x1a
+/* enum: Set MUM startup FUSE byte with extended delay */
+#define MC_CMD_AOE_OP_MUM_STARTUP_FUSE 0x1b
/* MC_CMD_AOE_OUT msgresponse */
#define MC_CMD_AOE_OUT_LEN 0
/* MC_CMD_AOE_IN_JTAG_WRITE msgrequest */
#define MC_CMD_AOE_IN_JTAG_WRITE_LENMIN 12
#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX 252
+#define MC_CMD_AOE_IN_JTAG_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_AOE_IN_JTAG_WRITE_LEN(num) (8+4*(num))
+#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4)
/* MC_CMD_AOE_IN_CMD_OFST 0 */
/* MC_CMD_AOE_IN_CMD_LEN 4 */
#define MC_CMD_AOE_IN_JTAG_WRITE_DATALEN_OFST 4
#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_LEN 4
#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MINNUM 1
#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM 61
+#define MC_CMD_AOE_IN_JTAG_WRITE_DATA_MAXNUM_MCDI2 253
/* MC_CMD_AOE_IN_FPGA_ACCESS msgrequest */
#define MC_CMD_AOE_IN_FPGA_ACCESS_LEN 8
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_LBN 0
#define MC_CMD_AOE_IN_FC_BOOT_CONTROL_BOOT_ENABLE_WIDTH 1
+/* MC_CMD_AOE_IN_MUM_STARTUP_FUSE msgrequest: On AOE2, set MUM startup FUSE
+ * byte with extended delay of 64ms. On some servers with noisy power rails,
+ * this ensures that the MUM IO pins do not show spurious transitions while the
+ * power rails are stabilising. Note that this operation requires a hard-
+ * powercycle to take effect. See bug76446.
+ */
+#define MC_CMD_AOE_IN_MUM_STARTUP_FUSE_LEN 4
+/* Must be MC_CMD_AOE_OP_MUM_STARTUP_FUSE */
+/* MC_CMD_AOE_IN_CMD_OFST 0 */
+/* MC_CMD_AOE_IN_CMD_LEN 4 */
+
/* MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO msgresponse */
#define MC_CMD_AOE_OUT_GET_FC_ASSERT_INFO_LEN 144
/* Assertion status flag. */
/* MC_CMD_AOE_OUT_FAN_FAILURES msgresponse */
#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMIN 4
#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX 252
+#define MC_CMD_AOE_OUT_FAN_FAILURES_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_FAN_FAILURES_LEN(num) (0+4*(num))
+#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_NUM(len) (((len)-0)/4)
/* Failure counts for each fan */
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_OFST 0
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_LEN 4
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MINNUM 1
#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM 63
+#define MC_CMD_AOE_OUT_FAN_FAILURES_COUNT_MAXNUM_MCDI2 255
/* MC_CMD_AOE_OUT_CPLD_REPROGRAM msgresponse */
#define MC_CMD_AOE_OUT_CPLD_REPROGRAM_LEN 4
/* MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO msgresponse */
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMIN 5
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX 252
+#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_LEN(num) (4+1*(num))
+#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_NUM(len) (((len)-4)/1)
/* in bytes */
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_OFST 0
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATALEN_LEN 4
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_LEN 1
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MINNUM 1
#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM 248
+#define MC_CMD_AOE_OUT_GET_PHY_MEDIA_INFO_DATA_MAXNUM_MCDI2 1016
/* MC_CMD_AOE_OUT_JTAG_WRITE msgresponse */
#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMIN 12
#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX 252
+#define MC_CMD_AOE_OUT_JTAG_WRITE_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_JTAG_WRITE_LEN(num) (8+4*(num))
+#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_NUM(len) (((len)-8)/4)
/* Used to align the in and out data blocks so the MC can re-use the cmd */
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_OFST 0
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATALEN_LEN 4
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_LEN 4
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MINNUM 1
#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM 61
+#define MC_CMD_AOE_OUT_JTAG_WRITE_DATA_MAXNUM_MCDI2 253
/* MC_CMD_AOE_OUT_FPGA_ACCESS msgresponse */
#define MC_CMD_AOE_OUT_FPGA_ACCESS_LEN 0
/* MC_CMD_AOE_OUT_DDR msgresponse */
#define MC_CMD_AOE_OUT_DDR_LENMIN 17
#define MC_CMD_AOE_OUT_DDR_LENMAX 252
+#define MC_CMD_AOE_OUT_DDR_LENMAX_MCDI2 1020
#define MC_CMD_AOE_OUT_DDR_LEN(num) (16+1*(num))
+#define MC_CMD_AOE_OUT_DDR_SPD_NUM(len) (((len)-16)/1)
/* Information on the module. */
#define MC_CMD_AOE_OUT_DDR_FLAGS_OFST 0
#define MC_CMD_AOE_OUT_DDR_FLAGS_LEN 4
#define MC_CMD_AOE_OUT_DDR_SPD_LEN 1
#define MC_CMD_AOE_OUT_DDR_SPD_MINNUM 1
#define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM 236
+#define MC_CMD_AOE_OUT_DDR_SPD_MAXNUM_MCDI2 1004
/* MC_CMD_AOE_OUT_SET_MTU_OFFSET msgresponse */
#define MC_CMD_AOE_OUT_SET_MTU_OFFSET_LEN 0
/* MC_CMD_AOE_OUT_FC_BOOT msgresponse */
#define MC_CMD_AOE_OUT_FC_BOOT_LEN 0
+/* MC_CMD_AOE_OUT_MUM_STARTUP_FUSE msgresponse */
+#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_LEN 4
+/* Current value of startup FUSE byte (fusebyte#4) read back after the update
+ * operation.
+ */
+#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_OFST 0
+#define MC_CMD_AOE_OUT_MUM_STARTUP_FUSE_READBACK_VALUE_LEN 4
+
#endif /* _SIENA_MC_DRIVER_PCOL_AOE_H */
-/*! \cidoxg_end */
git.droids-corp.org / dpdk.git / blobdiff