net/sfc/base: support different event descriptor sizes

[dpdk.git] / drivers / net / sfc / base / hunt_nic.c

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index b19b41e..054d4f4 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -20,7 +20,6 @@ hunt_nic_get_required_pcie_bandwidth(
        __out           uint32_t *bandwidth_mbpsp)
 {
        uint32_t port_modes;
-       uint32_t max_port_mode;
        uint32_t bandwidth;
        efx_rc_t rc;
 
@@ -30,13 +29,14 @@ hunt_nic_get_required_pcie_bandwidth(
         * capable mode is in use.
         */
 
-       if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
+       if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
+                   NULL, NULL)) != 0) {
                /* No port mode info available */
                bandwidth = 0;
                goto out;
        }
 
-       if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
+       if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
                /*
                 * This needs the full PCIe bandwidth (and could use
                 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
@@ -45,18 +45,14 @@ hunt_nic_get_required_pcie_bandwidth(
                            EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
                        goto fail1;
        } else {
-               if (port_modes & (1 << TLV_PORT_MODE_40G)) {
-                       max_port_mode = TLV_PORT_MODE_40G;
-               } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
-                       max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
+               if (port_modes & (1U << TLV_PORT_MODE_40G)) {
+                       bandwidth = 40000;
+               } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
+                       bandwidth = 4 * 10000;
                } else {
                        /* Assume two 10G ports */
-                       max_port_mode = TLV_PORT_MODE_10G_10G;
+                       bandwidth = 2 * 10000;
                }
-
-               if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
-                                                           &bandwidth)) != 0)
-                       goto fail2;
        }
 
 out:
@@ -64,8 +60,6 @@ out:
 
        return (0);
 
-fail2:
-       EFSYS_PROBE(fail2);
 fail1:
        EFSYS_PROBE1(fail1, efx_rc_t, rc);
 
@@ -78,22 +72,11 @@ hunt_board_cfg(
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
        efx_port_t *epp = &(enp->en_port);
-       uint32_t mask;
        uint32_t flags;
        uint32_t sysclk, dpcpu_clk;
        uint32_t bandwidth;
        efx_rc_t rc;
 
-       /* Huntington has a fixed 8Kbyte VI window size */
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP       == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP        == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP          == 8192);
-
-       EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
-       encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -200,33 +183,39 @@ hunt_board_cfg(
 
        encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 
+       /* Checksums for TSO sends can be incorrect on Huntington. */
+       encp->enc_bug61297_workaround = B_TRUE;
+
+       encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
+       encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
+       encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
        encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 
+       encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
+       encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
+       encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
+
        /*
         * The workaround for bug35388 uses the top bit of transmit queue
         * descriptor writes, preventing the use of 4096 descriptor TXQs.
         */
-       encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
+       encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ?
+           HUNT_TXQ_MAXNDESCS_BUG35388_WORKAROUND :
+           HUNT_TXQ_MAXNDESCS;
+       encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
 
        EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
        encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
        encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
        encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
 
-       /*
-        * Get the current privilege mask. Note that this may be modified
-        * dynamically, so this value is informational only. DO NOT use
-        * the privilege mask to check for sufficient privileges, as that
-        * can result in time-of-check/time-of-use bugs.
-        */
-       if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail5;
-       encp->enc_privilege_mask = mask;
-
        if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
-               goto fail6;
+               goto fail5;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 
        /* All Huntington devices have a PCIe Gen3, 8 lane connector */
@@ -234,8 +223,6 @@ hunt_board_cfg(
 
        return (0);
 
-fail6:
-       EFSYS_PROBE(fail6);
 fail5:
        EFSYS_PROBE(fail5);
 fail4: