net/qede: fix incorrect link status update

[dpdk.git] / drivers / net / sfc / base / hunt_nic.c

diff --git a/drivers/net/sfc/base/hunt_nic.c b/drivers/net/sfc/base/hunt_nic.c
index 14803c5..16ea81d 100644 (file)
--- a/drivers/net/sfc/base/hunt_nic.c
+++ b/drivers/net/sfc/base/hunt_nic.c
@@ -36,7 +36,7 @@ hunt_nic_get_required_pcie_bandwidth(
                goto out;
        }
 
-       if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
+       if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
                /*
                 * This needs the full PCIe bandwidth (and could use
                 * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
@@ -45,9 +45,9 @@ hunt_nic_get_required_pcie_bandwidth(
                            EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
                        goto fail1;
        } else {
-               if (port_modes & (1 << TLV_PORT_MODE_40G)) {
+               if (port_modes & (1U << TLV_PORT_MODE_40G)) {
                        max_port_mode = TLV_PORT_MODE_40G;
-               } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
+               } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
                        max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
                } else {
                        /* Assume two 10G ports */
@@ -83,16 +83,6 @@ hunt_board_cfg(
        uint32_t bandwidth;
        efx_rc_t rc;
 
-       /* Huntington has a fixed 8Kbyte VI window size */
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP       == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP        == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP          == 8192);
-
-       EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
-       encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are: