* capable mode is in use.
*/
- if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
+ if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
+ NULL, NULL)) != 0) {
/* No port mode info available */
bandwidth = 0;
goto out;
}
- if (port_modes & (1 << TLV_PORT_MODE_40G_40G)) {
+ if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
/*
* This needs the full PCIe bandwidth (and could use
* more) - roughly 64 Gbit/s for 8 lanes of Gen3.
EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
goto fail1;
} else {
- if (port_modes & (1 << TLV_PORT_MODE_40G)) {
+ if (port_modes & (1U << TLV_PORT_MODE_40G)) {
max_port_mode = TLV_PORT_MODE_40G;
- } else if (port_modes & (1 << TLV_PORT_MODE_10G_10G_10G_10G)) {
+ } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
} else {
/* Assume two 10G ports */
uint32_t bandwidth;
efx_rc_t rc;
- /* Huntington has a fixed 8Kbyte VI window size */
- EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP == 8192);
- EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP == 8192);
- EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP == 8192);
- EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP == 8192);
- EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP == 8192);
-
- EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K == 8192);
- encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
/*
* Enable firmware workarounds for hardware errata.
* Expected responses are:
encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
+ /* Checksums for TSO sends can be incorrect on Huntington. */
+ encp->enc_bug61297_workaround = B_TRUE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */