/* SPDX-License-Identifier: BSD-3-Clause
*
- * Copyright (c) 2015-2018 Solarflare Communications Inc.
- * All rights reserved.
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2015-2019 Solarflare Communications Inc.
*/
#include "efx.h"
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford2 */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+ encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
+ encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
+ encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
}
encp->enc_rx_buf_align_end = end_padding;
+ encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+ encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
+ encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
+ encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
+
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo