net/sfc: fix assert in set multicast address list

[dpdk.git] / drivers / net / sfc / base / medford2_nic.c

diff --git a/drivers/net/sfc/base/medford2_nic.c b/drivers/net/sfc/base/medford2_nic.c
index 85431d2..7f5ad17 100644 (file)
--- a/drivers/net/sfc/base/medford2_nic.c
+++ b/drivers/net/sfc/base/medford2_nic.c
@@ -49,26 +49,11 @@ medford2_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t end_padding;
        uint32_t bandwidth;
-       uint32_t vi_window_shift;
        efx_rc_t rc;
 
-       /*
-        * FIXME: Likely to be incomplete and incorrect.
-        * Parts of this should be shared with Huntington.
-        */
-
-       /* Medford2 has a variable VI window size (8K, 16K or 64K) */
-       if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
-               goto fail1;
-
-       EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
-       encp->enc_vi_window_shift = vi_window_shift;
-
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -109,11 +94,11 @@ medford2_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail2;
+               goto fail1;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail3;
+               goto fail2;
 
        /*
         * The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -129,7 +114,7 @@ medford2_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail4;
+                       goto fail3;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -148,16 +133,6 @@ medford2_board_cfg(
        encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
        encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
 
-       /*
-        * Get the current privilege mask. Note that this may be modified
-        * dynamically, so this value is informational only. DO NOT use
-        * the privilege mask to check for sufficient privileges, as that
-        * can result in time-of-check/time-of-use bugs.
-        */
-       if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail5;
-       encp->enc_privilege_mask = mask;
-
        /*
         * Medford2 stores a single global copy of VPD, not per-PF as on
         * Huntington.
@@ -166,16 +141,12 @@ medford2_board_cfg(
 
        rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail6;
+               goto fail4;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail6:
-       EFSYS_PROBE(fail6);
-fail5:
-       EFSYS_PROBE(fail5);
 fail4:
        EFSYS_PROBE(fail4);
 fail3: