__in efx_nic_t *enp,
__out uint32_t *bandwidth_mbpsp)
{
- uint32_t port_modes;
- uint32_t current_mode;
uint32_t bandwidth;
efx_rc_t rc;
/* FIXME: support new Medford2 dynamic port modes */
- if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
- ¤t_mode)) != 0) {
- /* No port mode info available. */
- bandwidth = 0;
- goto out;
- }
-
- if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
+ if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
&bandwidth)) != 0)
goto fail1;
-out:
*bandwidth_mbpsp = bandwidth;
return (0);
__in efx_nic_t *enp)
{
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
- uint32_t mask;
uint32_t sysclk, dpcpu_clk;
- uint32_t base, nvec;
uint32_t end_padding;
uint32_t bandwidth;
- uint32_t vi_window_shift;
efx_rc_t rc;
- /*
- * FIXME: Likely to be incomplete and incorrect.
- * Parts of this should be shared with Huntington.
- */
-
- /* Medford2 has a variable VI window size (8K, 16K or 64K) */
- if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
- goto fail1;
-
- EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
- encp->enc_vi_window_shift = vi_window_shift;
-
-
/*
* Enable firmware workarounds for hardware errata.
* Expected responses are:
encp->enc_bug41750_workaround = B_TRUE;
}
- /* Chained multicast is always enabled on Medford2 */
- encp->enc_bug26807_workaround = B_TRUE;
-
/*
* If the bug61265 workaround is enabled, then interrupt holdoff timers
* cannot be controlled by timer table writes, so MCDI must be used
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
- goto fail2;
+ goto fail1;
+
+ /* Checksums for TSO sends should always be correct on Medford2. */
+ encp->enc_bug61297_workaround = B_FALSE;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail3;
+ goto fail2;
/*
* The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
+ encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
+ encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
+ encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
- goto fail4;
+ goto fail3;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
}
encp->enc_rx_buf_align_end = end_padding;
- encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
- /* No boundary crossing limits */
- encp->enc_tx_dma_desc_boundary = 0;
+ encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+ encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
- /*
- * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
- * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
- * resources (allocated to this PCIe function), which is zero until
- * after we have allocated VIs.
- */
- encp->enc_evq_limit = 1024;
- encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
- encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
+ encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
+ encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo
* stuffing.
*/
- encp->enc_txq_max_ndescs = 2048;
-
- encp->enc_buftbl_limit = 0xFFFFFFFF;
+ encp->enc_txq_max_ndescs = MEDFORD2_TXQ_MAXNDESCS;
+ encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
- /*
- * Get the current privilege mask. Note that this may be modified
- * dynamically, so this value is informational only. DO NOT use
- * the privilege mask to check for sufficient privileges, as that
- * can result in time-of-check/time-of-use bugs.
- */
- if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
- goto fail5;
- encp->enc_privilege_mask = mask;
-
- /* Get interrupt vector limits */
- if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
- if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail6;
-
- /* Ignore error (cannot query vector limits from a VF). */
- base = 0;
- nvec = 1024;
- }
- encp->enc_intr_vec_base = base;
- encp->enc_intr_limit = nvec;
-
- /*
- * Maximum number of bytes into the frame the TCP header can start for
- * firmware assisted TSO to work.
- */
- encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
-
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail7;
+ goto fail4;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail7:
- EFSYS_PROBE(fail7);
-fail6:
- EFSYS_PROBE(fail6);
-fail5:
- EFSYS_PROBE(fail5);
fail4:
EFSYS_PROBE(fail4);
fail3:
git.droids-corp.org / dpdk.git / blobdiff