#if EFSYS_OPT_MEDFORD2
-static __checkReturn efx_rc_t
-efx_mcdi_get_rxdp_config(
- __in efx_nic_t *enp,
- __out uint32_t *end_paddingp)
-{
- efx_mcdi_req_t req;
- uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
- MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
- uint32_t end_padding;
- efx_rc_t rc;
-
- memset(payload, 0, sizeof (payload));
- req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
- req.emr_in_buf = payload;
- req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
- req.emr_out_buf = payload;
- req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
-
- efx_mcdi_execute(enp, &req);
- if (req.emr_rc != 0) {
- rc = req.emr_rc;
- goto fail1;
- }
-
- if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
- GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
- /* RX DMA end padding is disabled */
- end_padding = 0;
- } else {
- switch (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
- GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
- case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
- end_padding = 64;
- break;
- case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
- end_padding = 128;
- break;
- case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
- end_padding = 256;
- break;
- default:
- rc = ENOTSUP;
- goto fail2;
- }
- }
-
- *end_paddingp = end_padding;
-
- return (0);
-
-fail2:
- EFSYS_PROBE(fail2);
-fail1:
- EFSYS_PROBE1(fail1, efx_rc_t, rc);
-
- return (rc);
-}
-
static __checkReturn efx_rc_t
medford2_nic_get_required_pcie_bandwidth(
__in efx_nic_t *enp,
medford2_board_cfg(
__in efx_nic_t *enp)
{
- efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
- uint8_t mac_addr[6] = { 0 };
- uint32_t board_type = 0;
- ef10_link_state_t els;
- efx_port_t *epp = &(enp->en_port);
- uint32_t port;
- uint32_t pf;
- uint32_t vf;
uint32_t mask;
uint32_t sysclk, dpcpu_clk;
uint32_t base, nvec;
uint32_t end_padding;
uint32_t bandwidth;
+ uint32_t vi_window_shift;
efx_rc_t rc;
/*
* Parts of this should be shared with Huntington.
*/
- if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
+ /* Medford2 has a variable VI window size (8K, 16K or 64K) */
+ if ((rc = ef10_get_vi_window_shift(enp, &vi_window_shift)) != 0)
goto fail1;
- /*
- * NOTE: The MCDI protocol numbers ports from zero.
- * The common code MCDI interface numbers ports from one.
- */
- emip->emi_port = port + 1;
+ EFSYS_ASSERT3U(vi_window_shift, <=, EFX_VI_WINDOW_SHIFT_64K);
+ encp->enc_vi_window_shift = vi_window_shift;
- if ((rc = ef10_external_port_mapping(enp, port,
- &encp->enc_external_port)) != 0)
- goto fail2;
-
- /*
- * Get PCIe function number from firmware (used for
- * per-function privilege and dynamic config info).
- * - PCIe PF: pf = PF number, vf = 0xffff.
- * - PCIe VF: pf = parent PF, vf = VF number.
- */
- if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
- goto fail3;
-
- encp->enc_pf = pf;
- encp->enc_vf = vf;
-
- /* MAC address for this function */
- if (EFX_PCI_FUNCTION_IS_PF(encp)) {
- rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
-#if EFSYS_OPT_ALLOW_UNCONFIGURED_NIC
- /*
- * Disable static config checking for Medford NICs, ONLY
- * for manufacturing test and setup at the factory, to
- * allow the static config to be installed.
- */
-#else /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
- if ((rc == 0) && (mac_addr[0] & 0x02)) {
- /*
- * If the static config does not include a global MAC
- * address pool then the board may return a locally
- * administered MAC address (this should only happen on
- * incorrectly programmed boards).
- */
- rc = EINVAL;
- }
-#endif /* EFSYS_OPT_ALLOW_UNCONFIGURED_NIC */
- } else {
- rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
- }
- if (rc != 0)
- goto fail4;
-
- EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
-
- /* Board configuration */
- rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
- if (rc != 0) {
- /* Unprivileged functions may not be able to read board cfg */
- if (rc == EACCES)
- board_type = 0;
- else
- goto fail5;
- }
-
- encp->enc_board_type = board_type;
- encp->enc_clk_mult = 1; /* not used for Medford2 */
-
- /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
- if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
- goto fail6;
-
- /* Obtain the default PHY advertised capabilities */
- if ((rc = ef10_phy_get_link(enp, &els)) != 0)
- goto fail7;
- epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
- epp->ep_adv_cap_mask = els.els_adv_cap_mask;
/*
* Enable firmware workarounds for hardware errata.
if (EFX_PCI_FUNCTION_IS_VF(encp)) {
/*
- * Interrupt testing does not work for VFs. See bug50084.
- * FIXME: Does this still apply to Medford2?
+ * Interrupt testing does not work for VFs on Medford2.
+ * See bug50084 and bug71432 comment 21.
*/
encp->enc_bug41750_workaround = B_TRUE;
}
else if ((rc == ENOTSUP) || (rc == ENOENT))
encp->enc_bug61265_workaround = B_FALSE;
else
- goto fail8;
+ goto fail2;
/* Get clock frequencies (in MHz). */
if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
- goto fail9;
+ goto fail3;
/*
* The Medford2 timer quantum is 1536 dpcpu_clk cycles, documented for
encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
- /* Check capabilities of running datapath firmware */
- if ((rc = ef10_get_datapath_caps(enp)) != 0)
- goto fail10;
-
/* Alignment for receive packet DMA buffers */
encp->enc_rx_buf_align_start = 1;
/* Get the RX DMA end padding alignment configuration */
if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
if (rc != EACCES)
- goto fail11;
+ goto fail4;
/* Assume largest tail padding size supported by hardware */
end_padding = 256;
}
encp->enc_rx_buf_align_end = end_padding;
- /* Alignment for WPTR updates */
- encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
-
- /*
- * Maximum number of exclusive RSS contexts which can be allocated. The
- * hardware supports 64, but 6 are reserved for shared contexts. They
- * are a global resource so not all may be available.
- */
- encp->enc_rx_scale_max_exclusive_contexts = 58;
-
- encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
- /* No boundary crossing limits */
- encp->enc_tx_dma_desc_boundary = 0;
-
- /*
- * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
- * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
- * resources (allocated to this PCIe function), which is zero until
- * after we have allocated VIs.
- */
- encp->enc_evq_limit = 1024;
- encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
- encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo
*/
encp->enc_txq_max_ndescs = 2048;
- encp->enc_buftbl_limit = 0xFFFFFFFF;
-
+ EFX_STATIC_ASSERT(MEDFORD2_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
encp->enc_piobuf_limit = MEDFORD2_PIOBUF_NBUFS;
encp->enc_piobuf_size = MEDFORD2_PIOBUF_SIZE;
encp->enc_piobuf_min_alloc_size = MEDFORD2_MIN_PIO_ALLOC_SIZE;
* can result in time-of-check/time-of-use bugs.
*/
if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
- goto fail12;
+ goto fail5;
encp->enc_privilege_mask = mask;
/* Get interrupt vector limits */
if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
if (EFX_PCI_FUNCTION_IS_PF(encp))
- goto fail13;
+ goto fail6;
/* Ignore error (cannot query vector limits from a VF). */
base = 0;
encp->enc_intr_vec_base = base;
encp->enc_intr_limit = nvec;
- /*
- * Maximum number of bytes into the frame the TCP header can start for
- * firmware assisted TSO to work.
- */
- encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
-
/*
* Medford2 stores a single global copy of VPD, not per-PF as on
* Huntington.
rc = medford2_nic_get_required_pcie_bandwidth(enp, &bandwidth);
if (rc != 0)
- goto fail14;
+ goto fail7;
encp->enc_required_pcie_bandwidth_mbps = bandwidth;
encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
return (0);
-fail14:
- EFSYS_PROBE(fail14);
-fail13:
- EFSYS_PROBE(fail13);
-fail12:
- EFSYS_PROBE(fail12);
-fail11:
- EFSYS_PROBE(fail11);
-fail10:
- EFSYS_PROBE(fail10);
-fail9:
- EFSYS_PROBE(fail9);
-fail8:
- EFSYS_PROBE(fail8);
fail7:
EFSYS_PROBE(fail7);
fail6:
git.droids-corp.org / dpdk.git / blobdiff