net/sfc/base: support different event descriptor sizes

[dpdk.git] / drivers / net / sfc / base / medford_nic.c

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 6dc895f..01a3462 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -15,23 +15,13 @@ medford_nic_get_required_pcie_bandwidth(
        __in            efx_nic_t *enp,
        __out           uint32_t *bandwidth_mbpsp)
 {
-       uint32_t port_modes;
-       uint32_t current_mode;
        uint32_t bandwidth;
        efx_rc_t rc;
 
-       if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
-                                   &current_mode)) != 0) {
-               /* No port mode info available. */
-               bandwidth = 0;
-               goto out;
-       }
-
-       if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
+       if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
                                                    &bandwidth)) != 0)
                goto fail1;
 
-out:
        *bandwidth_mbpsp = bandwidth;
 
        return (0);
@@ -94,6 +84,9 @@ medford_board_cfg(
        else
                goto fail1;
 
+       /* Checksums for TSO sends can be incorrect on Medford. */
+       encp->enc_bug61297_workaround = B_TRUE;
+
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
                goto fail2;
@@ -106,6 +99,10 @@ medford_board_cfg(
        encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
                    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 
+       encp->enc_ev_desc_size = EF10_EVQ_DESC_SIZE;
+       encp->enc_rx_desc_size = EF10_RXQ_DESC_SIZE;
+       encp->enc_tx_desc_size = EF10_TXQ_DESC_SIZE;
+
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
 
@@ -119,12 +116,19 @@ medford_board_cfg(
        }
        encp->enc_rx_buf_align_end = end_padding;
 
+       encp->enc_evq_max_nevs = EF10_EVQ_MAXNEVS;
+       encp->enc_evq_min_nevs = EF10_EVQ_MINNEVS;
+
+       encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
+       encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
+
        /*
         * The maximum supported transmit queue size is 2048. TXQs with 4096
         * descriptors are not supported as the top bit is used for vfifo
         * stuffing.
         */
-       encp->enc_txq_max_ndescs = 2048;
+       encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
+       encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
 
        EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
        encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;