net/sfc/base: define max desc number for every EF10 NIC

[dpdk.git] / drivers / net / sfc / base / medford_nic.c

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index add0af0..171e39b 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -15,23 +15,13 @@ medford_nic_get_required_pcie_bandwidth(
        __in            efx_nic_t *enp,
        __out           uint32_t *bandwidth_mbpsp)
 {
-       uint32_t port_modes;
-       uint32_t current_mode;
        uint32_t bandwidth;
        efx_rc_t rc;
 
-       if ((rc = efx_mcdi_get_port_modes(enp, &port_modes,
-                                   &current_mode)) != 0) {
-               /* No port mode info available. */
-               bandwidth = 0;
-               goto out;
-       }
-
-       if ((rc = ef10_nic_get_port_mode_bandwidth(current_mode,
+       if ((rc = ef10_nic_get_port_mode_bandwidth(enp,
                                                    &bandwidth)) != 0)
                goto fail1;
 
-out:
        *bandwidth_mbpsp = bandwidth;
 
        return (0);
@@ -47,28 +37,11 @@ medford_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
-       uint32_t base, nvec;
        uint32_t end_padding;
        uint32_t bandwidth;
        efx_rc_t rc;
 
-       /*
-        * FIXME: Likely to be incomplete and incorrect.
-        * Parts of this should be shared with Huntington.
-        */
-
-       /* Medford has a fixed 8Kbyte VI window size */
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_RPTR_REG_STEP       == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_EVQ_TMR_REG_STEP        == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_RX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_DESC_UPD_REG_STEP    == 8192);
-       EFX_STATIC_ASSERT(ER_DZ_TX_PIOBUF_STEP          == 8192);
-
-       EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
-       encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -111,6 +84,9 @@ medford_board_cfg(
        else
                goto fail1;
 
+       /* Checksums for TSO sends can be incorrect on Medford. */
+       encp->enc_bug61297_workaround = B_TRUE;
+
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
                goto fail2;
@@ -136,62 +112,19 @@ medford_board_cfg(
        }
        encp->enc_rx_buf_align_end = end_padding;
 
-       encp->enc_tx_dma_desc_size_max = EFX_MASK32(ESF_DZ_RX_KER_BYTE_CNT);
-       /* No boundary crossing limits */
-       encp->enc_tx_dma_desc_boundary = 0;
-
-       /*
-        * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
-        * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
-        * resources (allocated to this PCIe function), which is zero until
-        * after we have allocated VIs.
-        */
-       encp->enc_evq_limit = 1024;
-       encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
-       encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
-
        /*
         * The maximum supported transmit queue size is 2048. TXQs with 4096
         * descriptors are not supported as the top bit is used for vfifo
         * stuffing.
         */
-       encp->enc_txq_max_ndescs = 2048;
-
-       encp->enc_buftbl_limit = 0xFFFFFFFF;
+       encp->enc_txq_max_ndescs = MEDFORD_TXQ_MAXNDESCS;
+       encp->enc_txq_min_ndescs = EF10_TXQ_MINNDESCS;
 
        EFX_STATIC_ASSERT(MEDFORD_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
        encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
        encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
        encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
 
-       /*
-        * Get the current privilege mask. Note that this may be modified
-        * dynamically, so this value is informational only. DO NOT use
-        * the privilege mask to check for sufficient privileges, as that
-        * can result in time-of-check/time-of-use bugs.
-        */
-       if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail4;
-       encp->enc_privilege_mask = mask;
-
-       /* Get interrupt vector limits */
-       if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
-               if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail5;
-
-               /* Ignore error (cannot query vector limits from a VF). */
-               base = 0;
-               nvec = 1024;
-       }
-       encp->enc_intr_vec_base = base;
-       encp->enc_intr_limit = nvec;
-
-       /*
-        * Maximum number of bytes into the frame the TCP header can start for
-        * firmware assisted TSO to work.
-        */
-       encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
-
        /*
         * Medford stores a single global copy of VPD, not per-PF as on
         * Huntington.
@@ -200,16 +133,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail6;
+               goto fail4;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail6:
-       EFSYS_PROBE(fail6);
-fail5:
-       EFSYS_PROBE(fail5);
 fail4:
        EFSYS_PROBE(fail4);
 fail3: