net/sfc/base: move PHY/link config to ef10 NIC board cfg

[dpdk.git] / drivers / net / sfc / base / medford_nic.c

diff --git a/drivers/net/sfc/base/medford_nic.c b/drivers/net/sfc/base/medford_nic.c
index 7840c33..afa6493 100644 (file)
--- a/drivers/net/sfc/base/medford_nic.c
+++ b/drivers/net/sfc/base/medford_nic.c
@@ -47,8 +47,6 @@ medford_board_cfg(
        __in            efx_nic_t *enp)
 {
        efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
-       ef10_link_state_t els;
-       efx_port_t *epp = &(enp->en_port);
        uint32_t mask;
        uint32_t sysclk, dpcpu_clk;
        uint32_t base, nvec;
@@ -71,16 +69,6 @@ medford_board_cfg(
        EFX_STATIC_ASSERT(1U << EFX_VI_WINDOW_SHIFT_8K  == 8192);
        encp->enc_vi_window_shift = EFX_VI_WINDOW_SHIFT_8K;
 
-       /* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
-       if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
-               goto fail1;
-
-       /* Obtain the default PHY advertised capabilities */
-       if ((rc = ef10_phy_get_link(enp, &els)) != 0)
-               goto fail2;
-       epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
-       epp->ep_adv_cap_mask = els.els_adv_cap_mask;
-
        /*
         * Enable firmware workarounds for hardware errata.
         * Expected responses are:
@@ -121,11 +109,11 @@ medford_board_cfg(
        else if ((rc == ENOTSUP) || (rc == ENOENT))
                encp->enc_bug61265_workaround = B_FALSE;
        else
-               goto fail3;
+               goto fail1;
 
        /* Get clock frequencies (in MHz). */
        if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
-               goto fail4;
+               goto fail2;
 
        /*
         * The Medford timer quantum is 1536 dpcpu_clk cycles, documented for
@@ -137,7 +125,7 @@ medford_board_cfg(
 
        /* Check capabilities of running datapath firmware */
        if ((rc = ef10_get_datapath_caps(enp)) != 0)
-               goto fail5;
+               goto fail3;
 
        /* Alignment for receive packet DMA buffers */
        encp->enc_rx_buf_align_start = 1;
@@ -145,7 +133,7 @@ medford_board_cfg(
        /* Get the RX DMA end padding alignment configuration */
        if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0) {
                if (rc != EACCES)
-                       goto fail6;
+                       goto fail4;
 
                /* Assume largest tail padding size supported by hardware */
                end_padding = 256;
@@ -197,13 +185,13 @@ medford_board_cfg(
         * can result in time-of-check/time-of-use bugs.
         */
        if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
-               goto fail7;
+               goto fail5;
        encp->enc_privilege_mask = mask;
 
        /* Get interrupt vector limits */
        if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
                if (EFX_PCI_FUNCTION_IS_PF(encp))
-                       goto fail8;
+                       goto fail6;
 
                /* Ignore error (cannot query vector limits from a VF). */
                base = 0;
@@ -226,16 +214,12 @@ medford_board_cfg(
 
        rc = medford_nic_get_required_pcie_bandwidth(enp, &bandwidth);
        if (rc != 0)
-               goto fail9;
+               goto fail7;
        encp->enc_required_pcie_bandwidth_mbps = bandwidth;
        encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 
        return (0);
 
-fail9:
-       EFSYS_PROBE(fail9);
-fail8:
-       EFSYS_PROBE(fail8);
 fail7:
        EFSYS_PROBE(fail7);
 fail6: